WO2023165044A1

WO2023165044A1 - Memory detection method, circuit, apparatus and device, and storage medium

Info

Publication number: WO2023165044A1
Application number: PCT/CN2022/097517
Authority: WO
Inventors: 陆天辰
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-03-01
Filing date: 2022-06-08
Publication date: 2023-09-07
Also published as: CN114582411A

Abstract

Provided in the present disclosure are a memory detection method, circuit, apparatus and device, and a storage medium. The memory detection method comprises: writing test data into at least some storage units of a memory; turning on word lines connected to the storage units; taking 2N storage units, which correspond to an even number of input and output pins, as a compression group, and reading target data stored in each storage unit in the compression group, wherein N is a positive integer; according to a preset processing method, performing an operation on the target data corresponding to the compression group, so as to determine detection information of the compression group; and according to the detection information, determining whether there are defects in the storage units in the compression group.

Description

Memory detection method, circuit, device, equipment and storage medium

This disclosure is based on the Chinese patent application with the application number 202210212388.6, the application date is March 1, 2022, and the application name is "memory detection method, circuit, device, equipment and storage medium", and the priority of the Chinese patent application is claimed , the entire content of this Chinese patent application is hereby incorporated by reference into this disclosure.

technical field

The disclosure relates to a memory detection method, circuit, device, equipment and storage medium.

Background technique

Before the chip leaves the factory, it usually needs to go through a series of tests before it can be used as a product, such as wafer test (Circuit Probing, referred to as CP test), final test (Final Test, referred to as FT test), etc. Among them, in the wafer test (CP test) stage, it is necessary to test the memory cell matrix of the memory chip, which is mainly to quickly detect faulty cells in the memory cell matrix, so as to quickly repair defects and avoid affecting subsequent manufacturing. The traditional detection method for the memory cell matrix can only perform detection operations of one row and one column, resulting in low testing efficiency, wasting a lot of time, and high testing costs.

Contents of the invention

The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The disclosure provides a memory detection method, circuit, device, equipment and storage medium.

A first aspect of the present disclosure provides a memory detection method, the memory detection method comprising:

writing test data into at least some of the memory cells of the memory;

opening a word line connected to the memory cell;

Using 2N storage units corresponding to an even number of input and output pins as a compression group, reading the target data stored in each storage unit in the compression group, wherein N is a positive integer;

Performing operations on the target data corresponding to the compression group according to a preset processing method to determine the detection information of the compression group;

According to the detection information, it is determined whether the storage unit in the compression group has a defect.

According to some embodiments of the present disclosure, the operation of the target data corresponding to the compression group according to a preset processing method to determine the detection information of the compression group includes:

According to a first preset method, target data belonging to two storage units corresponding to two different input and output pins are compared to obtain N pieces of comparison result information; wherein, the first preset method includes XOR logic operation;

Determine the detection information of the compression group according to the comparison result information.

According to some embodiments of the present disclosure, the determining the detection information of the compression group according to the comparison result information includes:

Inputting the N pieces of comparison result information into corresponding N transistors respectively;

dividing the N transistors into two comparison groups, and acquiring state information of the transistors in each comparison group;

determining the output information of the comparison group according to the state information of each of the transistors in each of the comparison groups;

According to the output information, the detection information of the compression group is determined.

According to some embodiments of the present disclosure, the transistor includes an NMOS transistor.

According to some embodiments of the present disclosure, the determining the detection information of the compression group according to the output information includes:

An NOR operation is performed on the output information of the two comparison groups, and the operation result is used as the detection information of the compression group.

According to some embodiments of the present disclosure, the determining whether the storage unit in the compression group has a defect according to the detection information includes:

When the operation result is low level, it is determined that the storage unit in the compression group is defective;

When the operation result is at a high level, it is determined that the storage unit in the compression group has no defect.

According to some embodiments of the present disclosure, the detection method also includes:

After each compression group completes detection, the comparison group is controlled to perform a reset operation.

The preset data stored in each of the storage units except the target data is cached, and the preset data is controlled not to participate in the process of reading the target data stored in each of the storage units.

A second aspect of the present disclosure provides a memory detection circuit, the memory detection circuit comprising:

A compression circuit, the compression circuit includes a first processing circuit, the first processing circuit, the first processing circuit is connected to an even number of input and output pins of the memory, and the input and output pins correspond to 2N of the memory storage units, the first processing circuit includes N logic gates, each of which is connected to the corresponding input and output pins of the two storage units, where N is a positive integer;

The detection circuit, the second processing circuit includes N transistors, the N transistors are respectively connected to the output terminals of the N logic gates of the first processing circuit, the N transistors are respectively two comparison groups, and the detection The circuit includes output terminals respectively corresponding to the two comparison groups;

A judging circuit, the judging circuit is connected to the corresponding output ends of the two comparison groups.

According to some embodiments of the present disclosure, the judging circuit includes a judging logic gate, and the judging logic gate is connected to output terminals respectively corresponding to the two comparison groups.

According to some embodiments of the present disclosure, the memory detection circuit further includes a reset circuit connected between the output terminal of the transistor corresponding to each comparison group and the input terminal of the judgment logic gate.

According to some embodiments of the present disclosure, the compression circuit further includes a latch connected to the even number of input and output pins.

According to some embodiments of the present disclosure, the detection circuit further includes a pre-charging circuit connected to the input terminal of the judging circuit for pre-charging the input terminal of the judging circuit to a high level.

A third aspect of the present disclosure provides a memory detection device, the memory detection device comprising:

A write module, configured to write test data into at least some of the storage units of the memory;

a control module, configured to open a word line connected to the memory unit;

A reading module, configured to use the 2N storage units corresponding to an even number of input and output pins as a compression group, and read the target data stored in each storage unit in the compression group, where N is positive integer;

A judging module, configured to determine detection information of the compression group according to a preset processing method and the target data;

The judging module is further configured to determine whether the storage unit in the compression group has a defect according to the detection information.

According to some embodiments of the present disclosure, the detection device further includes a reset module, configured to control the comparison group to perform a reset operation after each compression group completes the detection.

According to some embodiments of the present disclosure, the detection device further includes a buffer for buffering preset data stored in each of the storage units except the target data;

The control module is also used for:

Controlling that the preset data does not participate in the process of reading the target stored in each of the storage units.

A fourth aspect of the present disclosure provides a memory detection device, the memory detection device comprising:

processor;

memory for storing processor-executable instructions;

Wherein, the processor is configured to execute the memory detection method according to the first aspect.

According to a fifth aspect of the embodiments of the present disclosure, there is provided a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by the processor of the memory testing device, the memory testing device can perform the operations described in the first aspect. The memory detection method.

In the memory detection method, circuit, device, equipment and storage medium provided by the embodiments of the present disclosure, the problems of low operation efficiency, waste of time and waste of detection resources in the prior art during wafer testing are solved. Using the memory detection method of the present disclosure can improve the memory detection efficiency, shorten the detection time, save a lot of time for the subsequent manufacturing process, and save the test cost at the same time.

Other aspects will be apparent to others upon reading and understanding the drawings and detailed description.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to denote like elements. The drawings in the following description are some, but not all, embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

FIG. 1 is a flow chart of a memory detection method shown according to an exemplary embodiment;

Fig. 2 is a schematic diagram showing the connection between memory word lines and memory cells according to an exemplary embodiment;

Fig. 3a is a schematic diagram of a data input structure according to an exemplary embodiment;

Fig. 3b is a schematic diagram of a data input structure shown according to an exemplary embodiment;

Fig. 4a is a schematic diagram of a compression group according to an exemplary embodiment;

Fig. 4b is a schematic diagram of a compression group according to an exemplary embodiment;

Fig. 5a is a schematic diagram of a compression circuit shown according to an exemplary embodiment;

Fig. 5b is a schematic diagram of a detection circuit and a judgment circuit according to an exemplary embodiment

Fig. 6 is a schematic diagram of a compressed storage unit according to an exemplary embodiment;

Fig. 7 is a block diagram of a memory detection device according to an exemplary embodiment;

Fig. 8 is a block diagram of a memory detection device according to an exemplary embodiment.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments It is a part of the embodiments of the present disclosure, but not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present disclosure. It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.

Before the chip leaves the factory, it usually needs to go through a series of tests before it can be used as a product, such as using chip probes for wafer testing (Circuit Probing, CP testing for short), and final testing (Final Test, FT testing for short). Among them, in the wafer test (CP test) stage, it is necessary to test the memory cell matrix of the memory chip, which is mainly to quickly detect the problematic memory cells in the memory cell matrix, so as to quickly repair defects and avoid affecting subsequent processes.

For a write operation defined by the microelectronics product standard, only one row and one column can be operated. For a read operation, only 64-bit data can be read, resulting in low test efficiency. If the above reading operation is also used for testing in the wafer testing (CP testing) stage, a lot of time will be wasted and testing costs will be consumed. Therefore, it is necessary to design a memory detection method to perform this stage of testing, so as to detect the storage units in the entire memory faster.

An exemplary embodiment of the present disclosure provides a memory detection method. In the memory testing method, test data is first written into at least part of the memory cells. When reading data, the storage units are grouped according to the input and output pins, and the 2N storage units corresponding to the even number of input and output pins are used as a compression group, and the target data stored in the compression group is calculated to finally determine the compression The detection information of the group, and then determine whether the storage units in the compression group have defects according to the detection information. Since the storage units in the memory are divided into compressed groups for detection, a large number of storage units can be detected in one detection process, so that it is possible to quickly detect whether the storage units in the memory are defective. While ensuring the accuracy and reliability of the detection, Improve detection efficiency.

An exemplary embodiment of the present disclosure provides a memory detection method, as shown in FIG. 1, FIG. 1 shows a flow chart of a memory detection method provided according to an exemplary embodiment of the present disclosure, and FIGS. 2-8 are Schematic diagrams of various stages of the memory detection method, the memory detection method will be introduced below with reference to FIGS. 2-8 .

In the memory detection method of the present disclosure, this embodiment does not limit the semiconductor structure. The following will take dynamic random access memory (DRAM) as an example for introduction, but this embodiment is not limited thereto. The semiconductor structure in this embodiment is also Other configurations are possible.

As shown in FIG. 1, a memory detection method provided by an exemplary embodiment of the present disclosure includes the following steps:

S110. Writing test data into at least some storage units of the memory;

S120, opening a word line connected to the memory cell;

S130, using 2N storage units corresponding to an even number of input and output pins as a compression group, and reading the target data stored in each storage unit in the compression group, where N is a positive integer;

S140. Perform calculations on the target data corresponding to the compression group according to a preset processing method, and determine detection information of the compression group;

S150. According to the detection information, determine whether there is a defect in the storage unit in the compression group.

In step S110, since it is necessary to detect whether the memory cell can normally store data during the wafer test stage, that is, to detect whether the written data is consistent with the read data, therefore, before performing subsequent detection steps, it is necessary to first Writing test data into at least part of the storage units of the memory, and then reading the test data through subsequent steps, and then detecting whether the storage unit is defective by comparing the written test data with the read data.

When writing test data, it is necessary to determine which part of the storage unit in the memory is to be tested, and then write test data into this part of the storage unit. For example, it may be to test all the storage units of the memory, and write test data to all the storage units of the memory at the same time. For another example, some storage units of the memory may also be tested, and after the range of the storage units to be tested is determined, test data is written into the selected storage units.

With reference to shown in Fig. 2, test data is written in the storage unit that needs to be tested in memory earlier, in an example, selected 16 storage banks (bank) in the memory, i.e. storage bank 0 shown in Fig. 2 , Repository 1, Repository 2, ..., Repository 15. It should be noted that the storage unit is usually the smallest storage unit in the memory, and one bit of data is stored in each storage unit, and each storage bank contains many storage units, and each storage bank contains two storage blocks (half bank ), the amount of data stored in each storage block is half that of the repository. It should be noted that at least some of the storage units in step S110 may be storage units corresponding to a row of word lines in the storage block. When the compression group is subsequently compressed, the 64-bit data corresponding to a word line may be compressed into 1 bit. It is also possible to compress two 32bit data into 1bit.

In order to test whether there is a problem with the storage units in the 16 storage banks and whether data can be stored normally, the test data is written into each storage bank. For example, in the compressed mode, a row of word lines for each of the two memory blocks in each memory bank is activated by an activation command, that is, 32 word lines are opened to supply memory connected to each word line. The test data used in the detection process is pre-stored in the unit. Specifically, there are 16 storage banks in this embodiment, and each storage bank includes two storage blocks, so there are 32 storage blocks in total. The activation command activates a row of word lines in each storage block, and the activation command activates 32 word lines in total. Wire.

In order to improve test accuracy and convenience, when writing test data, it is necessary to ensure that the test data written in each port used to write test data is consistent. Referring to FIG. 2 , the ports for writing test data in this embodiment include a row address latch 111 , a command latch 112 and a bank address latch 113 . The row address latch 111, the command latch 112 and the memory bank address latch 113 can all receive instructions respectively, wherein the row address latch 111 is electrically connected to the first control module 100; the command latch 112 is connected to the command The decoder 114 is connected, and the command decoder 114 is electrically connected with the first control module 100 and the second control module 200 respectively; the memory bank address latch 113 is electrically connected with the memory bank address decoder 115, and the memory bank address decoder 115 is electrically connected with the second memory bank address decoder 115. The two control modules 200 are electrically connected. The input end of the row address latch 111 is connected to the third amplifier 01 , the input end of the command latch 112 is connected to the first amplifier 02 , and the input end of the bank address latch 113 is connected to the second amplifier 03 . Each amplifier is provided with a positive input terminal and a negative input terminal. The negative input terminal of each amplifier is a command and address reference voltage signal terminal. The positive input terminal of the third amplifier 01 is a voltage signal terminal of the row address signal. The positive input terminal of the first amplifier 02 is the voltage signal terminal of the activation command, and the positive input terminal of the second amplifier 03 is the voltage signal terminal of the address signal of the storage bank. The test data that needs to be written into the storage unit is written into the storage unit after passing through each of the above-mentioned ports.

In this embodiment, one word line in each of the 32 memory blocks in the 16 memory banks is opened by an activation command to ensure that each memory cell connected to the word line in the 32 memory blocks of the 16 memory banks is Write consistent test data, that is, ensure that the pulses received by each storage unit are the same, so as to avoid writing different test data and causing detection errors in the subsequent detection process, for example, the pulses written to each storage unit The inconsistency of the data will affect the subsequent judgment operation, thereby causing a misjudgment of whether the storage unit is faulty.

In step S120, as shown in FIG. 2, the first signal lines 311 are respectively electrically connected to the memory bank 0 to the memory bank 15, and the first signal lines 311 are also electrically connected to the first control module 100; the second signal lines 322 are respectively connected to The storage bank 0 is electrically connected to the storage bank 15 , and the second signal line 322 is also electrically connected to the second control module 200 . Wherein, the input terminals of the first control module 100 are respectively electrically connected with the row address latch 111 and the command decoder 114, and the first control module 100 is used for receiving the row address signal transmitted by the row address latch 111, and for receiving The activation command transmitted by the command decoder 114. The second control module is electrically connected to the command decoder 114 and the memory bank address decoder 115 respectively, and the second control module is used for receiving the memory bank address signal and the activation command.

Define the test data written into the storage unit to be read from the storage unit as the target data, and in the process of reading the target data, first open the first signal line electrically connected to the storage bank 0 to the storage bank 15 311 and the second signal line 322. Next, the activation command amplified by the first amplifier 02 is transmitted to the command latch 112 for latching, and then transmitted to the command decoder 114 by the command latch 112 , and then transmitted to the first control module 100 . When the first control module 100 receives the activation command sent by the command decoder 114, the first control module 100 outputs a control signal to the first signal line 311 to open each of the storage banks 0 to 15 (16 storage banks in total). The word line of a memory block in a memory bank, that is, open 16 word lines.

After the second control module 200 receives the activation command sent by the command decoder 114, the second control module 200 outputs a control signal to the second signal line 322, and opens the storage bank 0 to the storage bank 15 (a total of 16 storage banks). The word lines of another memory block in each bank, that is, 16 word lines are turned on. Therefore, in the compression mode, the control signal is output to the first signal line 311 through the first control module 100, and the control signal is output to the second control line 322 through the second control module 200 to open the storage bank 0 to the storage bank 15. The word lines of each memory block included in each memory bank, that is, a total of 32 word lines are turned on by an activation command.

In an exemplary embodiment, referring to FIG. 3a and FIG. 3b , and referring to FIG. 2 , in the storage unit of the storage library in this embodiment, in addition to storing test data, it is also possible to store data from storage library 0 to storage library Write other preset data except test data in the storage unit of 15. In order to prevent other preset data from being read when the target data is read, causing the read target data to be affected by other preset data, a decoder 330 is provided in this embodiment. The decoder 330 has a wide range of uses. The decoder is not only used for code conversion and digital display of the terminal, but also for data distribution, memory addressing, and combined control signals. In this embodiment, the input terminals of the decoder 330 are electrically connected to the row address latch 111, the command latch 112 and the memory bank address latch 113 respectively, and need to be written into memory banks 0 to 15 The test data and other preset data of the storage unit are different according to the source and function of the signal, and the data are transmitted from the row address latch 111, the command latch 112 and the memory bank address latch 113 to the decoder 330 respectively, Transmit to the storage units in the storage bank 0 to the storage bank 15 through the decoder 330 .

In some possible embodiments, as shown in FIG. 3 b and FIG. 2 , latches or flip-flops are set at the input and output pins 700 corresponding to memory bank 0 to memory bank 15 . In order to improve the reliability of data operation, a latch is provided at the input and output pin 700 of each storage unit, that is, the latch 341, the latch 342, ..., the latch 3416 shown in FIG. The number of registers is in one-to-one correspondence with the number of storage banks, wherein the corresponding input and output pins 700 of each storage bank are connected to the latch through one pin of a logic NOR gate, and the other pin of the logic NOR gate The pin is connected to the voltage terminal of the address signal of the memory bank.

Each latch is provided with an input port, an output port (that is, an output enable port), a reset port, and a latch activation command port. The latch activation command port is used to receive the latch activation command, and the latch latches the data after receiving the latch activation command. The reset port is used to receive a reset command. After receiving the reset command, the latch is reset, and the data input to it can be stored again. The output port of the latch is output enable. In this embodiment, the storage unit 0 is set correspondingly to the latch 341, the storage unit 1 is set correspondingly to the latch 342, ..., the storage unit 15 is set correspondingly to the latch 3416, and the test data is passed as shown in Fig. 3a The decoder 330 enters memory bank 0 to memory bank 15, and enters into the latch corresponding to the memory bank as shown in FIG. 3b for latching.

When the latch does not receive the latch activation command, its output port does not change with the input signal of the input port, and remains in the original state, and does not output the data input by the input port of the latch. When the latch receives the latch activation command, the output port will output data. As shown in Figure 3b, when the latch activation command port of the latch 341 to the latch 3416 does not receive the latch activation command, no matter what data is input to the input port of each latch, no It will be output from the output port of the latch, so as to save other preset data stored in the memory bank, without affecting the output state of the test data in the memory bank, and avoid other preset data stored in the memory bank from affecting the reading target data.

According to another embodiment of the present disclosure, no latch may be provided at the input and output pins 700 of memory bank 0 to memory bank 15 shown in FIG. 2 , and flip-flops may be provided. After the test data passes through the decoder 330 shown in FIG. 3 a , it can be written into memory banks 0 to 15 . Before the clock signal comes, the flip-flop will keep the output port of the flip-flop to output the data written from the input port unchanged. After receiving the clock signal, the flip-flop changes the state of the output port of the flip-flop, and outputs the data received by the flip-flop after receiving the clock signal from the output port of the flip-flop. Therefore, connecting the storage unit to the trigger not only ensures that the test data in the storage unit will not be affected by other preset data, but also ensures that the accuracy of the output data will not be affected by the structure of the storage unit itself after the test data is written into the storage unit. sex.

In step S130, as shown in FIGS. 4a and 4b, the DQ shown in FIGS. 4a and 4b is used to represent the input and output pins of the memory, as the data port for writing data into the storage unit. It can be applied to DDR3 DRAM, DDR4 DRAM, DDR5 DRAM and other memories. Among them, DRAM (Dynamic Random Access Memory) generally refers to dynamic random access memory. As shown in Figure 4a, data transmission with an external controller can be performed through 8 DQs. Referring to FIG. 2, there are 16 memory banks in total from memory bank 0 to memory bank 15, that is, 32 memory blocks. For the data writing of one row of word lines in one memory block, when the burst length (BL, Burst Length) is 8, the 8 data ports will input 64bit (bit) data. The 8 data ports correspond to one compression group 44 . bit is the data bit of the storage unit, as shown in Figure 4a, if the burst length is 8, one data port corresponds to 8 data bits, namely bit0, bit1, ..., bit7, that is, one data port DQ0 corresponds to bit0 to bit7, Another data port DQ1 corresponds to bit0 to bit7, and so on. Those skilled in the art can understand that the burst length is not limited thereto. For example, as shown in FIG. Another data port DQ1 corresponds to bit4 to bit7, and so on.

What needs to be explained here is that this embodiment takes memory bank 0 to memory bank 15 as an example, and the above-mentioned Figure 4a and Figure 4b use the data compression method of the data port of one word line of two memory blocks of one memory bank Be explained. In addition to using a burst length of 4 or 8 to form a compression group, in the implementation process, the target data stored in 2N storage units can be used as a compression group to divide the compression group, where N is a positive integer, such as N Can be 1, 2, 3, 4, etc.

As shown in FIGS. 4 a and 4 b , after forming multiple compression groups 44 , XOR comparison is performed on the information in the compression groups 44 , and every four ports are compressed into 1-bit data. When performing XOR comparison on the information in the compressed group 44, different comparison methods can be used. In an example, the data between the two compression groups 44 can be compared, for example, the data in DQ0 and DQ1 can be XORed to obtain the first result, and the data in DQ2 and DQ3 can be XORed to obtain the second result , and then XOR compares the first result and the second result to obtain the final result, and compresses the output operation result to 1 bit. In another example, each storage unit in each compression group 44 can be subjected to pairwise XOR operation, and each compression group outputs a comparison result A, that is, DQ0 outputs comparison result A0, and DQ1 outputs comparison result A1, to And so on. Then, perform an XOR operation on the comparison result A0 output by DQ0 and the comparison result A output by DQ1, and output the first result; after the data in DQ2 and DQ3 have undergone the above-mentioned similar processing, output the second result, and then the first result Perform an XOR comparison with the second result to obtain the final result, and compress the output operation result to 1 bit. Through the method in this embodiment, the test data stored in a large number of storage units can be divided into a relatively small number of compression groups 44, and then an XOR operation is performed on the compression groups 44, and finally the test data stored in the 2N storage units The stored target data is compressed to 1 bit, so as to realize the purpose of quickly detecting the storage unit.

Since only 64-bit information can be written or read when traditionally writing and reading data, during a data writing and reading operation, each detection can only be performed on the memory cells corresponding to a row of word lines , resulting in low detection efficiency. In this embodiment, one detection process, one activation command can simultaneously open the word lines in each of the 32 memory blocks, and each word line will output 64-bit information, so that in one write and read 2048-bit information can be obtained during operation, which greatly improves the detection efficiency during the detection process.

Referring to Fig. 4a and the compressed storage unit shown in Fig. 6, when the data in a compressed group 44 is 8 bits, the 64-bit data corresponding to a word line will be compressed to 2 bits, that is, a word line in a memory block The corresponding 64bit is compressed to 2bit. Then the information in each memory bank is compressed into 4 bits. In the embodiment shown in FIG. 6 , 16 memory banks, that is, 2048 bits of information in memory bank 0 to memory bank 15 are finally compressed into 64 bits. Specifically, storage bank 0 includes two storage blocks, each storage block is compressed to 2 bits, and each storage block includes compressed 4-bit data, and these 4-bit data are respectively marked as bit0' to bit3', then the storage bank 0 corresponds to the compressed bit0' to bit3' information, storage bank 1 corresponds to the compressed bit8' to bit11' information... By analogy, it can be known that storage bank 0 to storage unit 7 correspond to the compressed bit0 'to bit31'. Similarly, memory bank 8 to memory bank 15 also correspond to compressed bit0' to bit31', thus, among the 16 memory banks, memory bank 0 to memory bank 15 correspond to compressed 64-bit information, and the compressed The 64bit information can be read out with one command, and it is no longer necessary to write data or read data one row and one column multiple times for each storage bank, so as to achieve the purpose of quickly reading test data.

In step S140, the implementation process may include the following two steps:

S141. Compare target data in two storage units corresponding to two different input and output pins according to a first preset method, and obtain N pieces of comparison result information; wherein, the first preset method includes an XOR logic operation.

S142. Determine detection information of the compression group according to the comparison result information.

In step S141, an XOR logic operation is performed on each storage unit of each compression group, and a comparison result information is obtained according to the logic operation. The 816-bit data of each two data ports DQ in the compression group passes through the circuit shown in Figure 5a to realize the exclusive OR logic operation of two data bits and finally obtain the 8-bit compression group information. , and finally obtain a 32-bit comparison result through an XOR logic operation.

In step S142, as shown in FIG. 5b, input N comparison result information into corresponding N transistors respectively, divide N transistors into two comparison groups 444, and obtain state information of transistors in each comparison group 444 , according to the state information of each transistor in each comparison group 444, determine the output information of the comparison group 444, and determine the detection information of the compression group 44 according to the output information. Specifically, 16-bit data is input into the 16 transistors shown in FIG. 5b. The 16 transistors are divided into two comparison groups 444, and each comparison group 444 includes 8 transistors. The input end of one comparison group 444 is connected to the first inverter O4, and the input end of the other comparison group 444 is connected to the second inverter O5. In the process of reading target data, the first inverter O4 and the second inverter The input terminals of the inverter 05 both input a high-level read signal READT, and after being inverted by the first inverter 04 and the second inverter 05 , output a low-level signal READB to the two comparison groups 444 respectively.

Wherein, the transistor includes an NMOS transistor. When the comparison result information is output at a high level, the comparison result information is output at a low level through the NMOS transistor; when the comparison result information is at a low level, the comparison result information is output at a high level after passing through the NMOS transistor. . As in this embodiment, the comparison result information of the storage units in the compression group 44 is input into its corresponding transistors, and the transistors are divided into two comparison groups 444 as shown in FIG. 5b, and the comparison result information is output through the transistors, wherein, When the comparison result information output of the storage unit is all 0, the comparison result information is output as a high level after passing through the transistor. If a comparison result information output is 1, the transistor outputs a low level. Through the circuit shown in Figure 5b, it is divided into 8bits and one comparison group to perform two-two compression, and the total 16bits of the two compression groups are compressed into 1bit. For a row of word lines in a memory block, the 32 bits obtained through compression in Figure 5a are compressed to obtain a 2-bit comparison result. For 16 memory banks, that is, 32 memory blocks, 2048 bits are compressed into 64 bits.

In step S150, according to the detection information, it is determined whether there is a defect in the storage unit in the compression group. When the operation result is low level, it is determined that there is a defect in the storage unit in the compression group, and when the operation result is high level, it is determined that there is no defect in the storage unit in the compression group. In an exemplary embodiment, the detection information of the two comparison groups 444 is subjected to an NOR logic operation as shown in the judgment circuit 111 in FIG. When the operation result is at a high level, it is determined that the storage units in the compression group have no defects, thereby completing the rapid detection of the memory, saving the time wasted in the traditional method of individually performing data detection of one row and one column for each storage unit.

In addition, it should be noted that after the detection of each compression group is completed, the comparison group should be controlled to perform a reset operation, so as to delete the information in each detection process in the comparison group, which is convenient for multiple polarities, Rapid detection to achieve the effect of circular detection.

Referring to FIG. 5a and FIG. 5b , a memory detection circuit diagram is shown according to an exemplary embodiment. As shown in FIG. 5 a and FIG. 5 b , the memory detection circuit includes: a compression circuit 555 , a detection circuit 666 and a judgment circuit 111 . Referring to FIG. 5 a , the compression circuit 555 includes a first processing circuit 511 , and the first processing circuit 511 is connected to 2N storage units corresponding to an even number of input and output pins 700 (see FIG. 2 ) of the memory. Taking 8 input and output pins and a burst length of 8 as an example, the 8 input and output pins 700 correspond to 64 memory cells of a row of word lines in a memory block, that is, 64bit data, and the input and output pin DQ0 will output 8bit Data, respectively DQ0 BIT0, DQ0 BIT1 to DQ0 BIT7, for the input and output pin DQ1 will output 8bit data, respectively DQ1 BIT0, DQ1 BIT1 to DQ1 BIT7, and so on, for the input and output pin DQ7 will output 8bit data, They are DQ7 BIT0, DQ7 BIT1 to DQ7 BIT7.

Wherein, the first processing circuit 511 includes N logic gates, each logic gate is connected to two input and output pins corresponding to two storage units, and N is a positive integer, that is, one logic gate is used for each two storage units for logic judgment And output the logical result. The test data stored in the storage unit enters the logic gate of the first processing circuit 511 through an even number of output pins to quickly perform operations on the test data in the storage unit, such as compressing the data in 2N storage units into Nbit data, After passing through the compression circuit 555, that is, the 64-bit data of 64 memory cells corresponding to a row of word lines in a memory block can be compressed and output as 32-bit data.

The detection circuit 666 includes a second processing circuit 611, as shown in FIG. For the two comparison groups 444 , the detection circuit 666 also includes output terminals respectively corresponding to the two comparison groups 444 . The N transistors in the second processing circuit 611 are connected to the logic gate output terminals of the first processing circuit 511. After the test data is calculated by the first processing circuit 511, it directly enters the N transistors in the second processing circuit 611. The output information of two comparison groups 444 is formed after the outputs of the N transistors of the comparison group 444 . Wherein, the N transistors may be NMOS transistors for outputting the output information of the two comparison groups 444 . Since consistent data is pre-stored in the storage unit, after the exclusive OR logic operation is performed by the compression circuit 555, if the storage unit is normal, the compression circuit 555 will output a low-level signal, and the NMOS tube in the comparison group 444 will not be turned on; If the storage unit is abnormal, the compression circuit 555 will output a high-level signal, the NMOS transistor in the comparison group 444 will be turned on, and the comparison group 444 will output a low-level signal.

The judging circuit 111 is connected to the corresponding output terminals of the two comparison groups 444 , and finally judges the output information of the two comparison groups 444 . Wherein, in one embodiment of the present disclosure, the judging circuit 111 includes a NOT gate and a NOR gate, the corresponding output terminals of the two comparison groups 444 are respectively connected to a NOT gate, and the input terminals of the two NOT gates are connected to the NOR gate. The input terminal is used to make a final judgment on the output information of the two comparison groups 444 . When it is judged that the operation result is low level, it is determined that the storage unit in the compression group 44 has a defect, and when the operation result is high level, it is determined that the storage unit in the compression group 44 has no defect.

In an exemplary embodiment, as shown in FIG. 5b, the detection circuit further includes a reset circuit 333, and the reset circuit 333 is connected between the output terminal of the transistor corresponding to each comparison group 444 and the judgment logic gate of the judgment circuit 111. Reset The circuit 333 is used to reset the memory after each detection, so as to facilitate the next detection.

In an exemplary embodiment, the compression circuit 555 further includes a latch (refer to FIG. 3 b ), and the latch is connected to an even number of input and output pins 700 (refer to FIG. 2 ). The latch caches the data in the storage unit to ensure that other preset data does not participate in the process of reading the target data stored in each storage unit.

In an exemplary embodiment, the detection circuit further includes a pre-charging circuit 222, and the pre-charging circuit 222 is connected to the output terminal of each comparison group 444 and the input terminal of the judging circuit 111, and is used to reset the judging circuit 111 before the read operation. The input is precharged high. The pre-charging circuit 222 includes a PMOS transistor. During the pre-charging process, the gate terminal of the PMOS transistor is connected to a low level, and the PMOS transistor is turned on. During the read operation, the gate terminal of the PMOS transistor is connected to a high level, and the PMOS transistor is turned off. When the input terminals of the judging circuit 111 are all at a high level during the read operation, that is, when each NMOS transistor in the comparison group 444 is disconnected, the judgment result is high after the non-logic and OR non-logic operations of the judging circuit 111 Flat, that is, the storage unit corresponding to the comparison group 444 is correct. When any NMOS transistor in the comparison group 444 is turned on so that the output result of the comparison group 444 is low level, and the output of the two comparison groups 444 is low level after the non-logic and OR non-logic operations of the judgment circuit 111, then this situation It can be judged that the storage unit corresponding to the comparison group 444 is wrong.

FIG. 7 shows a memory detection device according to an exemplary embodiment, the device at least includes a writing module 210 , a control module 220 , a reading module 230 and a judging module 240 .

A writing module 210, configured to write test data into at least some storage units of the memory;

a control module 220 configured to open a word line connected to the memory cell;

The reading module 230 is configured to use 2N storage units corresponding to an even number of input and output pins as a compression group, and read the target data stored in each storage unit in the compression group, where N is a positive integer.

The judging module 240 is configured to determine the detection information of the compression group based on the preset processing method and target data. It is also configured to determine whether there is a defect in the storage unit in the compression group according to the detection information.

In an exemplary embodiment, the detection device further includes a reset module 250, configured to control the comparison group to perform a reset operation after each compression group completes the detection, so as to facilitate repeated and rapid cycle use.

In an exemplary embodiment, the detection device further includes a latch for buffering preset data stored in each of the storage units except the target data, and the control module 220 is also configured to control the preset data not to participate in The process of reading the target data stored in each storage unit.

Fig. 8 is a block diagram of a device for memory detection, that is, a computer device 400, according to an exemplary embodiment. For example, the computer device 400 may be provided as a terminal device. Referring to FIG. 6, a computer device 400 includes a processor 401, and the number of processors can be set to one or more as required. The computer device 400 also includes a memory 402 for storing instructions executable by the processor 401 , such as application programs. The number of memories can be set to one or more as required. It can store one or more applications. The processor 401 is configured to execute instructions to perform the above memory detection method.

Those skilled in the art should understand that the embodiments of the present disclosure may be provided as a method, an apparatus (device), or a computer program product. Accordingly, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data , including but not limited to RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can be used in Any other medium, etc. that stores desired information and can be accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media, as is well known to those skilled in the art.

In an exemplary embodiment, there is provided a non-transitory computer-readable storage medium including instructions, such as the memory 402 including instructions, which can be executed by the processor 401 of the device 400 to complete the above method. For example, the non-transitory computer readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, and the like.

A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of the memory testing device, the memory testing device can execute the memory testing method in the above-mentioned embodiments.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the present disclosure. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

Each embodiment or implementation manner in this specification is described in a progressive manner, each embodiment focuses on the differences from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

In the description of this specification, descriptions with reference to the terms "embodiments", "exemplary embodiments", "some implementations", "exemplary implementations", "examples" and the like mean that the descriptions are described in conjunction with the implementations or examples. A specific feature, structure, material, or characteristic is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, or in a specific orientation. construction and operation are therefore not to be construed as limitations on the present disclosure.

It can be understood that the terms "first", "second" and the like used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

In one or more drawings, like elements are indicated with like reference numerals. For the sake of clarity, various parts in the drawings are not drawn to scale. Also, some well-known parts may not be shown. For simplicity, the structure obtained after several steps can be described in one figure. In the following, many specific details of the present disclosure, such as structures, materials, dimensions, processing techniques and techniques of devices, are described for a clearer understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some or all of the technical features; these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present disclosure.

Industrial Applicability

In the memory detection method, circuit, device, device, and storage medium of the embodiments of the present disclosure, the test data is first written into at least some of the storage units, and when the data is read, the storage units are grouped according to the input and output pins, The 2N storage units corresponding to an even number of input and output pins are used as a compression group, and the target data stored in the compression group is calculated to finally determine the detection information of the compression group, and then determine whether the storage unit in the compression group exists according to the detection information defect. By including the memory detection method, circuit, device, equipment and storage medium of the present disclosure, the memory detection efficiency can be improved, the detection time can be shortened, a lot of time can be saved for the subsequent manufacturing process, and the test cost can be saved at the same time.

Claims

A detection method for a memory, the detection method comprising:

writing test data into at least some of the memory cells of the memory;

opening a word line connected to the memory cell;

Using 2N storage units corresponding to an even number of input and output pins as a compression group, reading the target data stored in each storage unit in the compression group, wherein N is a positive integer;

Performing operations on the target data corresponding to the compression group according to a preset processing method to determine the detection information of the compression group;

According to the detection information, it is determined whether the storage unit in the compression group has a defect.
The detection method according to claim 1, wherein said performing operations on the target data corresponding to the compression group according to a preset processing method to determine the detection information of the compression group includes:

According to a first preset method, target data belonging to two storage units corresponding to two different input and output pins are compared to obtain N pieces of comparison result information; wherein, the first preset method includes XOR logic operation;

Determine the detection information of the compression group according to the comparison result information.
The detection method according to claim 2, wherein said determining the detection information of the compression group according to the comparison result information includes:

Inputting the N pieces of comparison result information into corresponding N transistors respectively;

dividing the N transistors into two comparison groups, and acquiring state information of the transistors in each comparison group;

determining the output information of the comparison group according to the state information of each of the transistors in each of the comparison groups;

According to the output information, the detection information of the compression group is determined.
The detection method according to claim 3, wherein the transistor comprises an NMOS transistor.
The detection method according to claim 3, wherein said determining the detection information of the compression group according to the output information comprises:

An NOR operation is performed on the output information of the two comparison groups, and the operation result is used as the detection information of the compression group.
The detection method according to claim 5, wherein, according to the detection information, determining whether there is a defect in the storage unit in the compression group comprises:

When the operation result is low level, it is determined that the storage unit in the compression group is defective;

When the operation result is at a high level, it is determined that the storage unit in the compression group has no defect.
The detection method according to claim 3, said method further comprising:

After each compression group completes detection, the comparison group is controlled to perform a reset operation.
The detection method according to claim 1, said method further comprising:

The preset data stored in each of the storage units except the target data is cached, and the preset data is controlled not to participate in the process of reading the target data stored in each of the storage units.
A memory detection circuit, the memory detection circuit comprising:

A compression circuit, the compression circuit includes a first processing circuit, the first processing circuit is connected to an even number of input and output pins of the memory, the input and output pins correspond to 2N storage units of the memory, and the first A processing circuit includes N logic gates, each of which is connected to the corresponding input and output pins of the two storage units, where N is a positive integer;

The detection circuit, the second processing circuit includes N transistors, the N transistors are respectively connected to the output terminals of the N logic gates of the first processing circuit, the N transistors are divided into two comparison groups, and the detection The circuit includes output terminals respectively corresponding to the two comparison groups;

A judging circuit, the judging circuit is connected to the corresponding output ends of the two comparison groups.
The memory detection circuit according to claim 9, wherein the judging circuit comprises a judging logic gate, and the judging logic gate is connected to corresponding output terminals of the two comparison groups.
The memory detection circuit according to claim 10, wherein the memory detection circuit further comprises a reset circuit, the reset circuit is connected to the output end of the transistor corresponding to each comparison group and the judgment logic gate between the input terminals.
The memory detection circuit according to claim 9, wherein the compression circuit further comprises a latch connected to the even number of input and output pins.
The memory detection circuit according to claim 9, wherein the detection circuit further comprises a pre-charging circuit, the pre-charging circuit is connected to the input terminal of the judgment circuit, and is used for pre-charging the input terminal of the judgment circuit to be high level.
A memory detection device, the memory detection device comprising:

A write module, configured to write test data into at least some of the storage units of the memory;

a control module, configured to open a word line connected to the memory cell;

A reading module, configured to use the 2N storage units corresponding to an even number of input and output pins as a compression group, and read the target data stored in each storage unit in the compression group, where N is positive integer;

A judging module, configured to determine detection information of the compression group according to a preset processing method and the target data;

The judging module is further configured to determine whether the storage unit in the compression group has a defect according to the detection information.
The memory detection device according to claim 14, said detection device further comprising a reset module, configured to control the comparison group to perform a reset operation after each of the compression groups completes the detection.
The memory detection device according to claim 14, said detection device further comprising a buffer for buffering preset data stored in each of said storage units except said target data;

The control module is also used for:

Controlling that the preset data does not participate in the process of reading the target data stored in each of the storage units.
A memory detection device, the detection device comprising:

processor;

memory for storing processor-executable instructions;

Wherein, the processor is configured to execute the method according to any one of claims 1-8.
A computer-readable storage medium, when the instructions in the storage medium are executed by a processor, the processor can execute the method according to any one of claims 1 to 8.