CN117995253A

CN117995253A - Memory testing method, testing circuit and memory

Info

Publication number: CN117995253A
Application number: CN202211327237.1A
Authority: CN
Inventors: 孙圆圆; 王佳
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-27
Filing date: 2022-10-27
Publication date: 2024-05-07
Also published as: WO2024087469A1

Abstract

The embodiment of the disclosure provides a memory test method, a test circuit and a memory. Wherein the method comprises the following steps: acquiring a first write column address of test data to be written; at least two bit signals in the first writing column address are set as preset effective values, a second writing column address is obtained, and test data are written into a storage array of the memory based on the second writing column address; acquiring a reading address for reading test data, and reading the test data from the memory array based on the reading address; and compressing the read test data to obtain a test result of the memory array.

Description

Memory testing method, testing circuit and memory

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory testing method, a testing circuit, and a memory.

Background

Memory is a widely used device in electronic devices, such as dynamic random access memory (Dynamic Random Access Memory, DRAM). The memory generally comprises at least one memory block, and each memory block can comprise a plurality of memory cells arranged in an array. In practical application, the read-write function of each storage unit in the memory can be tested to obtain the test result of the memory. However, the process of testing the memory in the related art is time-consuming and has low testing efficiency.

Disclosure of Invention

The embodiment of the disclosure provides a memory test method, a test circuit and a memory.

In one aspect, an embodiment of the present disclosure provides a method for testing a memory, where the memory includes at least one memory block, and the memory block includes a memory array, and the method includes:

Acquiring a first write column address of test data to be written;

At least two signals in the first writing column address are set as preset effective values, a second writing column address is obtained, and the test data are written into the storage array based on the second writing column address;

acquiring a reading address for reading the test data, and reading the test data from the storage array based on the reading address;

and compressing the read test data to obtain a test result of the storage array.

In another aspect, embodiments of the present disclosure provide a test circuit comprising:

the writing module is used for setting at least two signals in the acquired first writing column address as preset effective values to obtain a second writing column address, and writing the test data into a storage array of the memory based on the second writing column address;

The reading module is used for acquiring a reading address for reading the test data and reading the test data from the storage array based on the reading address;

And the verification module is used for compressing the read test data to obtain a test result of the storage array.

In yet another aspect, an embodiment of the present disclosure provides a memory, including: at least one memory block, the memory block comprising a memory array therein; the test circuit described in any of the embodiments above.

In the embodiment of the disclosure, on one hand, at least two signals in a first writing column address are set to be preset effective values to obtain a second writing column address, and test data is written into a storage array based on the second writing column address, so that the second writing column address can comprise signals with at least two values as the effective values, and the test data can be written into a plurality of columns of storage units simultaneously based on the second writing column address, so that the writing efficiency of the test data can be improved, the efficiency of testing a memory can be improved, and the test time consumption is reduced; on the other hand, based on the reading address for reading the test data, the test data is read from the storage array, and the read test data is compressed to obtain the test result of the storage array, so that the test result of the storage array can be obtained more rapidly by compressing the read test data, the test efficiency can be further improved, and the test time consumption is reduced.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Fig. 1 is a schematic implementation flow chart of a memory testing method according to an embodiment of the disclosure;

fig. 2 is a schematic implementation flow chart of a memory testing method according to an embodiment of the disclosure;

Fig. 3 is a schematic implementation flow chart of a memory testing method according to an embodiment of the disclosure;

Fig. 4A is a schematic diagram of a composition structure of a test circuit according to an embodiment of the disclosure;

Fig. 4B is a schematic diagram of a connection structure of a group of first nand gates and a group of second nand gates connected in series in a test circuit according to an embodiment of the disclosure;

fig. 5 is a schematic implementation flow chart of a memory testing method according to an embodiment of the disclosure;

fig. 6 is a schematic diagram of a composition structure of a memory according to an embodiment of the disclosure.

Detailed Description

Exemplary implementations of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure of the disclosed embodiments to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail. In the following description reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or a different subset of all possible embodiments and can be combined with each other without conflict. In the following description, the terms "first", "second", "third" and the like are merely used to distinguish similar objects and do not represent a particular ordering of the objects, it being understood that the "first", "second", "third" may be interchanged with a particular order or sequence, as permitted, to enable embodiments of the disclosure described herein to be practiced otherwise than as illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the present disclosure provide a method for testing a memory, which may be performed by a test device, such as a test bench, that tests the memory, or by a test circuit in the memory, and the embodiments of the present disclosure are not limited in this respect. The memory may include at least one memory block including a memory array. Fig. 1 is a schematic implementation flow chart of a memory testing method according to an embodiment of the disclosure, as shown in fig. 1, the method includes the following steps S101 and S104:

step S101, a first write column address of test data to be written is obtained.

Here, the test data may be any suitable data for writing into the memory array to be tested to test the memory array. In implementation, the test data may be generated by a test machine or may be generated by a memory test logic built in a memory, which is not limited in this embodiment of the disclosure.

In some embodiments, the method may be performed by a built-In Self Test (Memory Bulid-In-Self Test, mbist) circuit In memory, and the Test data may be generated by a built-In memory Test logic circuit (e.g., a Test vector generation module In Mbist circuit) In memory during Mbist testing of the memory.

The first write column address is a column address corresponding to a memory cell to be written with test data in the memory array to be tested. In practice, the first write column address may be obtained from outside the test station or from outside the memory, or may be generated by test circuitry within the test station or within the memory, as the embodiments of the present disclosure are not limited in this regard.

Step S102, at least two signals in the first writing column address are set to be preset effective values, a second writing column address is obtained, and the test data are written into the storage array based on the second writing column address.

And the at least two signals in the first writing column address are set as preset effective values to obtain a second writing column address, so that test data can be written into the multi-column storage units at the same time based on the second writing column address, the writing efficiency of the test data can be improved, the efficiency of testing the memory can be improved, and the test time consumption is reduced. Here, the effective value may be preset according to the actual situation, may be 1 or 0, or may be a high level or a low level, which is not limited by the embodiment of the present disclosure.

In some embodiments, the bit signals in the first write column address may be independent of each other.

In some embodiments, each bit signal in the first write column address may include at least one bit column address signal and an inverted signal of each bit column address signal. In implementation, at least one bit of the column address signal may be used as the target column address signal, and the target column address signal in the first write column address and the inverted signal of the target column address signal may be set to an effective value, so as to obtain the second write column address.

For example, assume that the first write column address includes column address signals C0, C1, C2, C3, and inverted signals C0', C1', C2', C3' corresponding to the column address signals C0, C1, C2, C3, respectively; the memory may include 16 decoding circuits, taking an and gate circuit with 4 inputs as an example, each decoding circuit receives one bit of C0 and C0', one bit of C1 and C1', one bit of C2 and C2', and one bit of C3 and C3', and each decoding circuit performs an and operation on the received 4-bit signal, respectively, to control to obtain a write column selection control signal according to a result of the and operation; that is, when the 4-bit signals received by the decoding circuit are all 1, the result of the and operation is 1, the write column selection control signal output by the decoding circuit is an effective value, and at least one column of memory cells corresponding to the control of the write column selection control signal is selected; when at least one bit in the 4-bit signals received by the decoding circuit is 0, the sum operation result is 0, the writing column selection control signal output by the decoding circuit is an effective value, and at least one column of storage units correspondingly controlled by the writing column selection control signal is not selected; if C0 is the target column address signal, C0 and C0' may be set to 1, then in the obtained second write column address, C0C1C2C3 may become 1xxx, C0' also becomes 1, and C1', C2', and C3' are still the inverted signals of C1, C2, and C3, respectively, so after decoding the current second write column address, there will be 4-bit signals received by the two decoding circuits respectively that are all 1, and thus the write column selection control signals corresponding to the two decoding circuits respectively are all valid values, and therefore, the multiple columns of memory cells controlled by the two write column selection control signals will be written with test data at the same time.

Step S103, a reading address for reading the test data is obtained, and the test data is read from the storage array based on the reading address.

Here, the read address for reading the test data may be determined according to an actual test scenario. In some embodiments, the read address may include an address of a portion of a memory cell in a memory array of a portion of a memory block in a memory, an address of all memory cells in a memory array of a portion of a memory block in a memory, and an address of all memory cells in a memory array of all memory blocks in a memory, which is not limited by the embodiments of the present disclosure.

In some embodiments, the read address may include, but is not limited to, at least one of a read block address for identifying a memory block where a memory cell to be read is located, a read row address for identifying a row where a memory cell to be read is located, a read column address for identifying a column where a memory cell to be read is located, and the like. For example, in the case where the read address includes a read block address, test data in all memory cells in a memory block corresponding to the read block address may be read; in the case where the read address includes a read row address, test data in each memory cell corresponding to the read row address in all memory blocks in the memory may be read; in the case where the read address includes a read column address, test data in each memory cell corresponding to the read column address in all memory blocks in the memory may be read; in the case that the read address includes a read block address and a read row address, test data in each memory cell corresponding to the read row address in a memory block corresponding to the read block address in the memory may be read; in the case where the read address includes a read block address, a read row address, and a read column address, test data in a memory cell in the memory determined by the read block address, the read row address, and the read column address may be read.

In implementation, the read address may be obtained from an external portion of the test machine or an external portion of the memory, or the read address may be generated by a test circuit within the test machine or the memory, or the read address may be default, which is not limited by embodiments of the present disclosure.

And step S104, compressing the read test data to obtain a test result of the storage array.

Here, the read test data with multiple bit numbers can be compressed to a smaller bit number through compression processing, so that the test result of the storage array is obtained, the bit number of the obtained test result is smaller than that of the read test data, and therefore whether the storage array currently tested is abnormal or not can be determined more quickly according to the test result with the smaller bit number.

In some embodiments, the test result may be any suitable information that can characterize whether an abnormality exists in the currently tested storage array, and according to the test result, whether the abnormality exists in the currently tested storage array may be directly determined. For example, the test result may be a signal "1" indicating that an anomaly exists in the currently tested storage array or a signal "0" indicating that no anomaly exists in the currently tested storage array. As another example, the test result may be information "false" indicating that an abnormality exists in the currently tested storage array or information "true" indicating that no abnormality exists in the currently tested storage array.

In some embodiments, the test result may be at least one bit of compressed data after the read test data is compressed, and by comparing the compressed data with preset target data, it may be determined whether an abnormality exists in the currently tested storage array. For example, in the case that the compressed data is consistent with the preset target data, it may be determined that there is no abnormality in the currently tested storage array; and under the condition that the compressed data is inconsistent with the preset target data, determining that the currently tested storage array is abnormal.

In practice, the read test data may be compressed in any suitable manner, which embodiments of the present disclosure are not limited in this regard. In some embodiments, the compression of the test data can be achieved by processing the data of each bit in the read test data according to the set logic, so as to obtain the test result. The set logic process may include, but is not limited to, at least one of exclusive or process, logical and process, and the like.

It should be noted that, because the memory cells, the data writing circuit and the data reading circuit in the memory may have anomalies, resulting in differences between the read test data and the written test data, the read test data is not necessarily identical to the written test data, and the test result may be indicative of whether the read test data is correct, i.e. whether the tested memory array has anomalies.

In the embodiment of the disclosure, on one hand, at least two signals in a first writing column address are set to be preset effective values to obtain a second writing column address, and test data can be written into a plurality of columns of storage units at the same time based on the second writing column address, so that the writing efficiency of the test data can be improved, the efficiency of testing a memory can be improved, and the test time consumption is reduced; on the other hand, based on the reading address for reading the test data, the test data is read from the storage array, and the read test data is compressed to obtain the test result of the storage array, so that the test result of the storage array can be obtained more rapidly by compressing the read test data, the test efficiency can be further improved, and the test time consumption is reduced.

In some embodiments, the first write column address comprises at least one bit of a column address signal and an inverse of each of the column address signals, wherein at least one bit of the column address signal is a target column address signal. The step S102 of setting at least two bits of signals in the first write column address to a preset valid value to obtain a second write column address may include the following steps S111 to S112:

step S111, obtain the compressed write instruction.

Here, the compact write instruction may be any suitable instruction for indicating whether to write test data (i.e., compact write) to a plurality of columns of memory cells in a memory array at a time. For example, the press abbreviation may be indicated by the instruction "1" and not indicated by the instruction "0"; or the instruction "0" indicates that the press abbreviation is performed, and the instruction "1" indicates that the press abbreviation is not performed. For another example, the instruction "11" may indicate that the press abbreviation is performed, and the instruction "00", "01", or "10" indicates that the press abbreviation is not performed; alternatively, the instruction "11", "01" or "10" may indicate that the press abbreviation is performed, and the instruction "00" indicates that the press abbreviation is not performed.

In implementation, the compression write instruction may be preset in a register, may be acquired from outside the test machine or outside the memory, or may be generated by a test circuit inside the test machine or inside the memory, which is not limited by the embodiment of the present disclosure.

Step S112, based on the compressed write command, sets the target column address signal and the inverted signal of the target column address signal in the first write column address to the valid value, so as to obtain a second write column address.

Here, the first write column address may include at least one bit of a column address signal and an inverted signal of each column address signal. For example, the first write column address includes column address signals C0, C1, C2, C3, and inverted signals C0', C1', C2', C3' corresponding to the column address signals C0, C1, C2, C3, respectively; if C0 is the target column address signal, both C0 and C0' will be set to 1, and in the resulting second write column address, C0C1C2C3 will become 1xxx, C0' will also become 1, and C1', C2', C3' will still be the inverted signals of C1, C2, C3, respectively.

The target column address signal in the first write column address may be any of the column address signals. In practice, one skilled in the art may select an appropriate target column address signal from among the column address signals of the first write column address according to actual circumstances, which is not limited by the embodiments of the present disclosure.

In some embodiments, the target column address signal in the first write column address and the inverted signal of the target column address signal may be set to valid values in the event that the compress write instruction indicates a compress write.

In some embodiments, the first write column address may be directly used as the second write column address without changing the column address signals in the first write column address and the inverted signal of each column address signal if the compress write instruction indicates that the compress write is not performed.

In the above embodiment, based on the compressed write instruction, the target column address signal in the first write column address and the inverted signal of the target column address signal are set to the valid values, so that whether to write test data into a plurality of columns of memory cells in the memory array at a time can be conveniently and flexibly controlled by the compressed write instruction, thereby improving the flexibility of testing the memory. For example, in the process of testing the memory, a compression writing instruction for indicating compression writing is used for starting a compression writing mode for improving the testing efficiency; and in the process of testing the memory, the compression writing instruction which indicates that compression writing is not performed is used for closing the compression writing mode, so that the writing stability of test data is improved, and the reliability of a test result is improved.

Fig. 2 is a schematic implementation flow chart of a memory testing method according to an embodiment of the disclosure, as shown in fig. 2, the method may include the following steps S201 to S206:

step S201, a first write column address of test data to be written is obtained.

Step S202, at least two signals in the first writing column address are set as preset effective values, and a second writing column address is obtained.

Here, the steps S201 to S202 correspond to the steps S101 to S102, and the embodiments of the steps S101 to S102 may be referred to in the implementation.

Step S203, decoding the second write column address to obtain at least two write column selection control signals.

At least two bits of signals in the second writing column address are preset effective values, at least two effective writing column selection control signals can be obtained simultaneously after the second writing column address is decoded, and each writing column selection control signal can control the selection state (namely selected or unselected) of at least one column of storage units; writing the column selection control signal as an effective value, and selecting at least one corresponding column of memory cells so as to write test data into the at least one column of memory cells; the write column selection control signal is an invalid value, and at least one corresponding column of memory cells is not selected, so that test data cannot be written into at least one column of memory cells correspondingly controlled by the write column selection control signal. In this way, since at least two bit signals in the second write column address are valid values, at least two valid write column selection control signals can be obtained at the same time after the second write column address is decoded, so that test data can be written into a plurality of columns of memory cells controlled by the at least two valid write column selection control signals at a time in the writing process.

In implementation, the second write column address may be decoded by a column address decoder in the test machine or a column address decoding circuit in the memory, to obtain at least two write column selection control signals corresponding to the second write column address.

Step S204, writing the test data into the memory array based on the at least two write column selection control signals.

Here, the test data may be written into at least two columns of memory cells controlled by at least two write column selection control signals corresponding to the second write column address. In implementation, test data may be written into a part of or all of the rows in at least two columns of memory cells controlled by at least two write column selection control signals corresponding to the second write column address, which is not limited by the embodiments of the present disclosure.

Step S205, acquiring a read address for reading the test data, and reading the test data from the memory array based on the read address.

And S206, compressing the read test data to obtain a test result of the storage array.

Here, the steps S205 to S206 correspond to the steps S103 to S104, and the embodiments of the steps S103 to S104 may be referred to when they are performed.

In the embodiment of the disclosure, the second writing column address is decoded, so that at least two writing column selection control signals corresponding to the second writing column address can be obtained, and test data can be simply and rapidly written into at least two columns of storage units in the storage array based on the at least two writing column selection control signals corresponding to the second writing column address, thereby improving the data writing efficiency in the test process and saving the test time.

In some embodiments, the step S201 may include the following step S211:

Step S211, obtaining a write address of test data to be written, where the write address includes a write row address and the first write column address.

The step S204 may include step S212:

Step S212, writing the test data into the memory array based on the write row address and the at least two write column selection control signals.

Here, the write row address may be used to determine the row in which the memory cells to be written with test data are located. In this way, based on the write row address and the at least two write column selection control signals, test data can be written simply and quickly into a plurality of memory cells in the memory array corresponding to the at least two write column selection control signals and the write row address.

In some embodiments, the step S212 may include the following steps S221 to S222:

step S221, turning on the current word line based on the write row address.

Here, each write row address may correspond to at least one word line in the memory, and at least one word line corresponding to the write row address may be turned on based on the acquired write row address.

Step S222, writing the test data into the memory cells on the current word line controlled by the at least two write column selection control signals.

Here, at least one row of memory cells in the memory array may be connected to each word line, each memory cell in each row of memory cells being located in a different column, and each write column selection control signal in the memory array may control at least one column of memory cells in the memory array. In this way, when the current word line in the memory array is in the on state, based on at least two write column selection control signals corresponding to the second write column address, test data can be written at a time into a plurality of memory cells controlled by the at least two write column selection control signals among at least one row of memory cells connected to the current word line.

In some embodiments, the above method may further include the following step S231:

step S231, updating the first write column address until the test data is written in all the memory cells on the current word line.

At least one update may be performed on the first write column address, so that at least two signals in the updated first write column address are set to a preset effective value, an updated second write column address is obtained, and test data is written into the memory array based on the updated second write column address until the test data is written into all memory cells on the current word line corresponding to the write row address.

In practice, a person skilled in the art may update the first write column address in any suitable update manner according to the actual situation, which is not limited by the embodiment of the present disclosure.

In some embodiments, the at least two bit signals in the first write column address include at least one bit column address signal and an inverted signal of each bit column address signal; in the process of setting at least two bit signals in the first write column address to a valid value, at least one bit of the target column address signal in the first write column address and an inverted signal of each of the target column address signals may be set to a valid value. In this way, the updated first writing column address can be obtained by updating other column address signals except for each target column address signal in the first writing column address, and then the updated second writing column address can be obtained, so that all storage units on the current word line in the storage array can be not repeatedly traversed, and test data can be written into each storage unit on the current word line in the storage array without being repeatedly written, and then the writing efficiency of the test data in the test process can be further improved, and the test time is saved.

Fig. 3 is a schematic implementation flow chart of a memory testing method according to an embodiment of the disclosure, as shown in fig. 3, the method may include the following steps S301 to S304:

in step S301, a first write column address of test data to be written is obtained.

Step S302, at least two signals in the first write column address are set to a preset valid value, so as to obtain a second write column address, and the test data is written into the memory array based on the second write column address.

Step S303, a reading address for reading the test data is obtained, and the test data is read from the storage array based on the reading address.

Here, the steps S301 to S303 correspond to the steps S101 to S103, and the embodiments of the steps S101 to S103 may be referred to when they are performed.

And step S304, performing exclusive OR processing on the read test data to obtain a test result of the storage array.

Here, the data of each bit in the test data may be subjected to exclusive or processing, to obtain a test result of the memory array. Therefore, the compression of the read test data can be simply and efficiently realized, and the test efficiency can be improved.

In some embodiments, the step S304 may include the following step S311:

Step S311, performing exclusive-or processing on the read test data with data of each preset bit number as a group, and performing exclusive-or processing on the result after each group of exclusive-or processing again until the test result of one bit is obtained.

Here, the preset number of bits may be preset by those skilled in the art according to actual circumstances. For example, the preset number of bits may be 8, 16, 32, or 64, etc.

When in implementation, the read test data can be grouped into a group of data with each preset bit number; performing exclusive-or processing on the data of each bit in each group of data aiming at the data of each group of preset bit number to obtain a result after exclusive-or processing of the group of data; and carrying out exclusive-or processing on the results after exclusive-or processing of each group again until a one-bit test result is obtained.

In some embodiments, the preset number of bits is 32 bits.

In the above embodiment, the read test data is exclusive-ored by taking the data of each preset bit number as a group, and exclusive-ored is performed again on the result after exclusive-ored of each group until a one-bit test result is obtained, so that the compression of the read test data can be efficiently realized, and the test efficiency is further improved.

The embodiment of the present disclosure provides a test circuit, and fig. 4A is a schematic diagram of a composition structure of the test circuit provided in the embodiment of the present disclosure, as shown in fig. 4A, the test circuit 400 includes: a write module 410, a read module 420, and a verify module 430, wherein:

A writing module 410, configured to set at least two signals in the obtained first writing column address to a preset valid value, obtain a second writing column address, and write the test data into a storage array of the memory based on the second writing column address;

A reading module 420, configured to obtain a reading address for reading the test data, and read the test data from the storage array based on the reading address;

and the verification module 430 is configured to perform compression processing on the read test data to obtain a test result of the storage array.

In the embodiment of the disclosure, on one hand, at least two signals in a first writing column address are set to be preset effective values through a writing module to obtain a second writing column address, and test data is written into a storage array based on the second writing column address, so that the second writing column address can comprise signals with the at least two values as the effective values, and the test data can be written into at least two columns of storage units in the storage array simultaneously based on the second writing column address, so that the writing efficiency of the test data can be improved, the efficiency of testing a memory can be improved, and the test time consumption is reduced; on the other hand, the reading module reads the test data from the storage array based on the reading address for reading the test data, and the verification module compresses the read test data to obtain the test result of the storage array, so that the test result of the storage array can be obtained more rapidly, the test efficiency can be further improved, and the test time consumption is reduced.

In some embodiments, the first write column address comprises at least one bit of a column address signal and an inverse of each of the column address signals, wherein at least one bit of the column address signal is a target column address signal; the write module includes: an address conversion unit configured to: and acquiring a compressed write instruction, and setting the target column address signal in the first write column address and the inverted signal of the target column address signal as the effective value based on the compressed write instruction to obtain a second write column address.

In some embodiments, the effective value is 1, the address conversion unit includes at least one group of conversion subunits respectively corresponding to each target column address signal, and each conversion subunit includes a first NAND gate and a second NAND gate connected in cascade; wherein,

The first NAND gate is used for: receiving an instruction signal corresponding to a compression write instruction and a target column address signal corresponding to a conversion subunit to which the first NAND gate belongs, and determining a value output after NAND processing the instruction signal and the target column address signal as a converted inverted signal of the target column address signal;

The second NAND gate is used for: and receiving the command signal and the converted inverted signal of the target column address signal output by the first NAND gate, and determining the value of the command signal and the converted inverted signal of the target column address signal after NAND processing as the converted target column address signal.

Here, the first write column address includes at least one target column address signal, and for each target column address signal, a set of first nand gates and second nand gates connected in cascade may be used to set a bit of the target column address signal in the first write column address and an inverted signal of the target column address signal to be a valid value of 1, so as to obtain a converted first write column address, that is, a second write column address.

Fig. 4B is a schematic diagram of a connection structure of a group of first nand gates and second nand gates connected in cascade in a test circuit according to an embodiment of the present disclosure, as shown in fig. 4B, the first nand gate 411 has a first input terminal I1, a second input terminal I2, and a first output terminal O1, the second nand gate 412 has a third input terminal I3, a fourth input terminal I4, and a second output terminal O2, wherein the first output terminal O1 is connected to the third input terminal I3, the first input terminal I1 is connected to a target column address signal CA, the second input terminal I2 and the fourth input terminal I4 are both connected to an instruction signal ComCA corresponding to a compressed write instruction, and a signal output by the first output terminal O1 of the first nand gate 411 is used as a converted inverted signal #ca 'of the target column address signal, and a signal output by the second output terminal O2 of the second nand gate 412 is used as a converted target column address signal CA'; thus, in the case where the command signal ComCA is "0", the converted target column address signal CA 'and the converted inverted signal #ca' are both 1, regardless of whether the target column address signal CA is "0" or "1"; in the case where the command signal ComCA is "1", the converted target column address signal CA 'is identical to the original target column address signal CA, and the converted inverted signal #ca' is opposite to the original target column address signal CA.

In the above embodiment, the first write column address signal and the inverted signal of the first write column address signal can be set to the valid value simply and efficiently by the first nand gate and the second nand gate connected in cascade.

In some embodiments, the write module includes: the decoding unit is used for decoding the second write column address to obtain at least two write column selection control signals; and a writing unit for writing the test data into the memory array based on the at least two write column selection control signals.

In some embodiments, the write module further comprises: a first acquiring unit, configured to acquire a write address of test data to be written, where the write address includes a write row address and the first write column address.

In some embodiments, the memory array includes at least one memory cell arranged in an array; the writing unit is further configured to: opening a current word line based on the write row address; the test data is written into a plurality of memory cells on the current word line controlled by the at least two write column selection control signals.

In some embodiments, the write module further comprises: and the updating unit is used for updating the first writing column address until the test data are written in all the storage units on the current word line.

In some embodiments, the verification module is further to: and performing exclusive OR processing on the read test data to obtain a test result of the storage array.

In some embodiments, the verification module is further to: and carrying out exclusive-or processing on the read test data by taking the data with each preset bit number as a group, and carrying out exclusive-or processing on the result after each group of exclusive-or processing again until the test result with one bit is obtained.

In some embodiments, the preset number of bits is 32 bits.

It should be noted that, the functions or the modules included in the test circuit provided by the embodiments of the present disclosure may be used to perform the method described in the method embodiments, and the specific implementation of the test circuit may refer to the description of the method embodiments, which has similar beneficial effects as the method embodiments.

The application of the test method provided by the embodiment of the present disclosure in an actual scenario is described below by taking a Mbist test scenario of a memory as an example.

In Mbist test scenarios, the test vectors (i.e., test data) for the memory are not generated by an external test machine, but are automatically generated by built-in memory test logic (i.e., mbist circuitry) in the memory, and the built-in memory test logic may also perform a comparison of the results. The Mbist circuit comprises a test vector generation module, a control module and a response analysis module. When the control module of Mbist circuit receives the instruction to start testing, the test vector generation module starts to generate and output test data, and calculates the output expected value of the memory, while the control module of Mbist circuit will continuously perform read-write operation on the storage units in the memory at equal intervals, which usually takes a long time.

On the basis, the method for testing the memory provided by the embodiment of the disclosure adopts the operations of compressing and inputting and compressing and reading in the process of testing the memory, so that the testing time can be greatly reduced, and the testing efficiency is improved.

In the method for testing the memory provided by the embodiment of the disclosure, after the control module of the Mbist circuit receives the instruction for starting the test, the Mbist test is started, the input and output of the memory are switched to the test module of the memory, and the test vector of the test module is automatically generated by the test vector generation module of the Mbist circuit; the control module also calculates the output expected value of the memory, when the memory receives the test vector, the memory executes the read-write operation at equal intervals, traverses all addresses of the memory array in the memory to access the read-write function of all memory cells, and finally reads and records the address with the error in the memory array through the mode register, so that the memory cells with the error in the read-write can be repaired in a mPPR (memory Post PACKAGE REPAIR, memory package Post repair) mode. In the process of testing the memory, the Mbist circuit needs to access different addresses in the memory, read-write operation is needed to be executed on the different addresses, and the read data is compared with expected data through the response analysis module, so that a test result is obtained. In the embodiment of the disclosure, in the process of writing data, the same data can be written into all storage blocks (banks), and in the process of reading out the data, exclusive or comparison (compression reading) can be performed on each 32bit of data in the read test data, so as to obtain a test result; if the test result indicates that the read-write of the data has errors, an error mark can be reported; in this way, test time can be saved to a great extent. In the process of writing data, the Mbist circuit can also write data in a compression and abbreviated mode and read data in a compression and read mode, so that the test cost and the test time are saved.

In some embodiments, during the process of writing data, at least one bit of the first writing column address signal generated by the Mbist circuit and the inverted signal of the column address signal may be forcedly set to 1, so as to obtain the second writing column address signal. In this way, when the second write column address is decoded (i.e., column decoded), two or more column selection control signals can be simultaneously turned on, thereby increasing the write speed.

In some embodiments, the test data written into the memory may be from a preset register in the Mbist circuit, in which a portion of the test data may be fixedly stored, and the response analysis module may compare the read test data with the test data stored in the register, to obtain a test result.

Fig. 5 is a schematic implementation flow chart of a method for testing a memory according to an embodiment of the present disclosure, as shown in fig. 5, the method may be executed by Mbist circuits, and includes the following steps S501 to S505:

Step S501, starting Mbist test;

step S502, traversing each row address and column address of a storage array in each storage block of the memory to be tested, so as to write the same test data into each storage unit in each storage block;

step S503, refreshing data in the memory array in each memory block;

Here, since it takes a long time to cycle through each row address and column address of the memory array in each memory block of the memory to be tested, it is necessary to reduce the leakage in the memory array by the refresh operation, improving the test stability.

Step S504, traversing and reading test data stored in a storage array of each storage block in the memory to be tested, performing exclusive OR processing on the test data read in the storage array of each storage block to obtain a test result of the storage array, and recording an address with an error in reading and writing into a mode register of the memory based on the test result;

In step S505, it is detected whether there is an address record of a read-write error in the mode register of the memory.

According to the method for testing the memory, the compression abbreviation input mode and the compression reading mode are adopted in the Mbist testing process, so that the testing time can be shortened to a great extent, and the testing time cost is saved.

An embodiment of the present disclosure provides a memory, and fig. 6 is a schematic diagram of a composition structure of the memory provided in the embodiment of the present disclosure, as shown in fig. 6, the memory 600 includes: at least one memory block 610, wherein the memory block 610 includes a memory array 611; test circuit 400 as described in any of the embodiments above.

It should be noted that, the memory provided in the embodiments of the present disclosure includes the test circuit in the test circuit embodiment, and the specific implementation of the test circuit may refer to the description of the test circuit embodiment, which has similar beneficial effects as the test circuit embodiment.

The embodiment of the disclosure also provides a test device, which comprises: a processor, configured to execute some or all of the steps in the above embodiment of the memory testing method; a memory for storing executable instructions for execution by the processor. The processor may also be referred to as a CPU (Central Processing Unit ). The processor may be an integrated circuit chip having signal processing capabilities. The Processor may also be a general purpose Processor, a digital signal Processor (DIGITAL SIGNAL Processor, DSP), an Application SPECIFIC INTEGRATED Circuit (ASIC), a Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. In addition, the processor may be commonly implemented by an integrated circuit chip.

The disclosed embodiments provide a computer readable storage medium, which when executed by a processor, enables the processor to perform some or all of the steps in the memory test method embodiments described above. Here, the storage medium may include: a U-disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes. Thus, embodiments of the present disclosure are not limited to any specific hardware, software, or firmware, or any combination of the three.

The above description of various embodiments is intended to emphasize the differences between the various embodiments, the same or similar features being referred to each other.

In several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and methods may be implemented in a non-targeted manner. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

While the foregoing is directed to embodiments of the present disclosure, the scope of the embodiments of the present disclosure is not limited to the foregoing, and any changes and substitutions that are within the scope of the embodiments of the present disclosure will be readily apparent to those skilled in the art.

Claims

1. A method of testing a memory, wherein the memory includes at least one memory block, the memory block including a memory array therein, the method comprising:

Acquiring a first write column address of test data to be written;

2. The method of claim 1, wherein the first write column address comprises at least one bit of a column address signal and an inverse of each of the column address signals, wherein at least one bit of the column address signal is a target column address signal;

The step of setting at least two signals in the first writing column address as preset effective values to obtain a second writing column address includes:

Acquiring a compression writing instruction;

And setting the target column address signal and the inverted signal of the target column address signal in the first writing column address as the effective values based on the compression writing instruction to obtain a second writing column address.

3. The method of claim 1, wherein the writing the test data into the storage array based on the second write column address comprises:

decoding the second write column address to obtain at least two write column selection control signals;

the test data is written into the memory array based on the at least two write column select control signals.

4. A method according to claim 3, wherein said obtaining a first write column address for test data to be written comprises:

Acquiring a write address of test data to be written, wherein the write address comprises a write row address and the first write column address;

the writing the test data into the memory array based on the at least two write column select control signals includes:

The test data is written into the memory array based on the write row address and the at least two write column select control signals.

5. The method of claim 4, wherein the writing the test data into the memory array based on the write row address and the at least two write column select control signals comprises:

Opening a current word line based on the write row address;

The test data is written into a plurality of memory cells on the current word line controlled by the at least two write column selection control signals.

6. The method of claim 5, wherein the method further comprises:

Updating the first write column address until the test data is written in all memory cells on the current word line.

7. The method according to any one of claims 1 to 6, wherein the compressing the read test data to obtain the test result of the storage array includes:

And performing exclusive OR processing on the read test data to obtain a test result of the storage array.

8. The method of claim 7, wherein xoring the read test data to obtain a test result of the memory array, comprises:

And carrying out exclusive-or processing on the read test data by taking the data with each preset bit number as a group, and carrying out exclusive-or processing on the result after each group of exclusive-or processing again until the test result with one bit is obtained.

9. The method of claim 8, wherein the predetermined number of bits is 32 bits.

10. A test circuit, comprising:

11. The test circuit of claim 10, wherein the first write column address comprises at least one bit of a column address signal and an inverse of each of the column address signals, wherein at least one bit of the column address signal is a target column address signal;

The write module includes:

An address conversion unit configured to: and acquiring a compressed write instruction, and setting the target column address signal in the first write column address and the inverted signal of the target column address signal as the effective value based on the compressed write instruction to obtain a second write column address.

12. The test circuit of claim 11, wherein the effective value is 1, the address translation unit includes at least one set of translation subunits respectively corresponding to each target column address signal, each translation subunit including a first nand gate and a second nand gate connected in cascade; wherein,

13. The test circuit of claim 10, wherein the write module comprises:

the decoding unit is used for decoding the second write column address to obtain at least two write column selection control signals;

and a writing unit for writing the test data into the memory array based on the at least two write column selection control signals.

14. The test circuit of claim 13, wherein the write module further comprises: a first acquiring unit, configured to acquire a write address of test data to be written, where the write address includes a write row address and the first write column address.

15. The test circuit of claim 14, wherein the memory array comprises at least one memory cell arranged in an array; the writing unit is further configured to:

Opening a current word line based on the write row address;

16. The test circuit of claim 15, wherein the write module further comprises:

And the updating unit is used for updating the first writing column address until the test data are written in all the storage units on the current word line.

17. The test circuit of any one of claims 10 to 16, wherein the verification module is further configured to: and performing exclusive OR processing on the read test data to obtain a test result of the storage array.

18. The test circuit of claim 17, wherein the verification module is further configured to: and carrying out exclusive-or processing on the read test data by taking the data with each preset bit number as a group, and carrying out exclusive-or processing on the result after each group of exclusive-or processing again until the test result with one bit is obtained.

19. The test circuit of claim 18, wherein the predetermined number of bits is 32 bits.

20. A memory, comprising:

at least one memory block, the memory block comprising a memory array therein;

a test circuit as claimed in any one of claims 10 to 19.