CN212516572U - Repair circuit and memory - Google Patents

Abstract

The embodiment of the application relates to a repair circuit and a memory, wherein the repair circuit comprises: a plurality of redundant memory cells, each redundant memory cell configured with a status signal; the repair module is respectively connected with the plurality of redundant storage units and used for determining a target storage unit from the plurality of redundant storage units according to the plurality of state signals and repairing the defective storage unit through the target storage unit; the target storage unit corresponds to the defective storage units one by one, the repair module can repair different defective storage units in a plurality of repair stages respectively, and the plurality of repair stages share a plurality of redundant storage units. By selecting a target memory cell in response to a status signal of a redundant memory cell and sharing the redundant memory cell at a plurality of repair stages, the repair rate and the repair flexibility of a defective memory cell are improved, i.e., a repair circuit having higher repair flexibility and reliability is provided.

Description

Repair circuit and memory

Technical Field

The embodiment of the application relates to the technical field of semiconductor devices, in particular to a repair circuit and a memory.

Background

A semiconductor memory is a memory that is accessed using a semiconductor circuit, and is widely used in various fields due to its fast storage speed and high integration. In order to achieve greater flexibility and reliability, a certain number of redundant memory cells are typically provided in the memory to replace the normal memory cells when they are damaged. However, as the number of normal memory cells increases, the number of existing redundant memory cells cannot meet the repair requirement of the memory, and the repair rate of the defective memory cells is insufficient.

SUMMERY OF THE UTILITY MODEL

In view of the above, it is necessary to provide a repair circuit and a memory for solving the problem of insufficient repair rate of defective memory cells.

A repair circuit, comprising:

a plurality of redundant memory cells, each of the redundant memory cells configured with a status signal;

the repair module is respectively connected with the plurality of redundant storage units and is used for determining a target storage unit from the plurality of redundant storage units according to the plurality of state signals and repairing a defective storage unit through the target storage unit;

the target memory cells correspond to the defective memory cells one to one, the repair module can repair different defective memory cells in a plurality of repair stages respectively, and the repair stages share the redundant memory cells.

In one embodiment, the repair module comprises:

a selection unit for generating a unit selection signal according to the plurality of status signals;

and the storage repairing unit is respectively connected with the selection unit and the plurality of redundant storage units, and is used for receiving the unit selection signal, determining the target storage unit according to the unit selection signal, and repairing the defective storage unit through the target storage unit.

In one embodiment, the selection unit is configured to generate the unit selection signal according to a preset repair order and a plurality of the status signals.

In one embodiment, the unit selection signal comprises a plurality of enable signals, the enable signals correspond to the redundant storage units one by one, and at most one of the enable signals is enabled at the same time;

the selection unit comprises a plurality of generating circuits, and each generating circuit is used for correspondingly generating one enabling signal;

the storage repair unit is used for determining the redundant storage unit corresponding to the enable signal with valid enable as the target storage unit.

In one embodiment, the status signal carries occupation information of the corresponding redundant memory cell, the occupation information includes occupied and unoccupied, the selection unit includes a first generation circuit, the first generation circuit is configured to generate a first enable signal, and the redundant memory cell in a first repair order is defined as a first redundant memory cell; wherein the content of the first and second substances,

when the first redundant memory cell is occupied, the first enabling signal is disabled; the first enable signal is active when the first redundant memory cell is not occupied.

In one embodiment, the redundant memory cells in the n-th repair order are defined as n-th redundant memory cells, n is a positive integer greater than 1, and the selection unit further comprises an n-th generation circuit for generating an n-th enable signal; wherein the content of the first and second substances,

when at least one of all the redundant storage repair units in the repair sequence before the nth redundant storage unit is unoccupied, enabling the nth enable signal to be invalid; and when all the redundant storage repair units in the repair sequence before the nth redundant storage unit are occupied and the nth redundant storage unit is not occupied, enabling the nth enable signal to be effective.

In one embodiment, the nth generation circuit includes:

n-1 first logic gates, wherein the n-1 first logic gates are used for receiving the n-1 state signals in a one-to-one correspondence manner and carrying out logic calculation on the received state signals;

the second logic gate is provided with n input ends and an output end, the n-1 input ends are respectively connected with the output ends of the n-1 first logic gates in a one-to-one correspondence mode, the rest input ends are used for receiving nth state signals, and the second logic gate is used for carrying out logic calculation on a plurality of input signals so as to generate the nth enable signal.

In one embodiment, the first logic gate is a not gate, and the second logic gate is an and gate.

In one embodiment, a plurality of the generating circuits share at least a part of the first logic gate.

In one embodiment, the plurality of repair phases includes a first repair phase and a second repair phase, and the memory repair unit includes:

the first repair unit is respectively connected with the selection unit and the plurality of redundant memory units and is used for repairing the defective memory unit in the first repair stage;

the second repair unit is respectively connected with the selection unit and the plurality of redundant memory units and is used for repairing the defective memory unit in the second repair stage;

wherein the first repair phase is earlier than the second repair phase, and the first repair unit occupies the redundant memory cell in preference to the second repair unit.

In one embodiment, the first repair phase is a post-package repair phase and the second repair phase is a self-repair phase.

In one embodiment, the method further comprises the following steps:

the detection module is used for detecting the operating states of the normal storage units and determining the defective storage unit from the normal storage units according to the operating states.

A memory, comprising:

a plurality of normal memory cells;

as described above, the repair circuits are connected to the plurality of normal memory cells, respectively;

wherein the normal memory cell with abnormal operation state is used as the defect memory cell.

The repair circuit and the memory described above, the repair circuit including: a plurality of redundant memory cells, each of the redundant memory cells configured with a status signal; the repair module is respectively connected with the plurality of redundant storage units and is used for determining a target storage unit from the plurality of redundant storage units according to the plurality of state signals and repairing a defective storage unit through the target storage unit; the target memory cells correspond to the defective memory cells one to one, the repair module can repair different defective memory cells in a plurality of repair stages respectively, and the repair stages share the redundant memory cells. By selecting a target memory cell in response to a status signal of a redundant memory cell and sharing the redundant memory cell at a plurality of repair stages, the repair rate and the repair flexibility of a defective memory cell are improved, i.e., a repair circuit having higher repair flexibility and reliability is provided.

Drawings

Fig. 1 is a schematic structural diagram of a repair circuit of the first embodiment;

FIG. 2 is a schematic structural diagram of a repair circuit according to a second embodiment;

FIG. 3 is a schematic structural diagram of a repair circuit according to a third embodiment;

FIG. 4 is a schematic structural diagram of a repair circuit according to a fourth embodiment;

FIG. 5 is a schematic structural diagram of a repair circuit of the fifth embodiment;

fig. 6 is a schematic structural diagram of a repair circuit of the sixth embodiment.

Element number description:

redundant memory cell: 10; a first redundant memory cell: 11; a second redundant memory cell: 12; a third redundant memory cell: 13; a fourth redundant memory cell: 14; a repair module: 20; a selection unit: 100, respectively; a generation circuit: 110; a first generation circuit: 111; a second generation circuit: 112, a first electrode; the third generating circuit: 113; a fourth generation circuit: 114, and a carrier; a first logic gate: 1101; a second logic gate: 1102; a storage repair unit: 200 of a carrier; a first repair unit: 210; a detection module: 30.

Detailed Description

To facilitate an understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. The embodiments of the present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application belong. The terminology used herein in the description of the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the embodiments of the present application, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only used for convenience in describing the embodiments of the present application and simplifying the description, but do not indicate or imply that the devices or elements referred to must have specific orientations, be constructed in specific orientations, and be operated, and thus, should not be construed as limiting the embodiments of the present application.

Fig. 1 is a schematic structural diagram of a repair circuit according to a first embodiment, which is used to repair a defective memory cell in a memory. The memory may be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like. The memory comprises a plurality of normal storage units, and each normal storage unit can store data, so that the storage function of the memory is realized by the plurality of normal storage units together.

However, it is understood that there may be various conditions such as poor manufacturing process or device aging during the manufacturing and using processes of the memory, and the operating state of the normal memory cell is abnormal. The exception of the operating state may include, for example, that data cannot be written, that written data cannot be read correctly, and the like. When the above problem occurs in the normal memory cell, it can be identified as a defective memory cell. The defective memory cells cannot perform an access function, and thus need to be repaired by a repair circuit. Moreover, even if the normal memory cell is in a normal operating state when shipped from a factory, damage may occur during use, thereby turning into a defective memory cell. That is, a plurality of repair stages are required to repair different defective memory cells, which are originally and newly generated, respectively, so as to improve the memory operation efficiency and the read/write accuracy. Referring to fig. 1, in the present embodiment, a repair circuit includes a repair module 20 and a plurality of redundant memory cells 10.

A plurality of redundant memory cells 10, each of the redundant memory cells 10 configured with a status signal. The status signal carries corresponding occupancy information of the redundant memory cell 10, that is, the status signal corresponds to the occupancy information of the redundant memory cell 10, and the occupancy information includes occupied and unoccupied. Herein, the occupation refers to repair of a defective memory cell by the redundant memory cell 10. The repair means that when data is read and written, the redundant memory cell 10 is used to replace the defective memory cell, and the data read and write functions that should be executed by the defective memory cell are executed, and the defective memory cell is still set at the original address, but the read and write operations are not required to be executed by the defective memory cell. When a defective memory cell is found, the repair of the defective memory cell can be achieved by replacing the defective memory cell with the redundant memory cell 10 through a repair process. After the defective memory cell is repaired, the data to be stored in the defective memory cell is stored in the redundant memory cell 10, and if the data in the defective memory cell needs to be read, the data is read from the corresponding redundant memory cell 10.

Illustratively, the repair may include a row repair in which a row address corresponding to a defective memory cell is replaced by a row address of the redundant memory cell 10 and/or a column repair in which a column address corresponding to a defective memory cell is replaced by a column address of the redundant memory cell 10.

Moreover, when the redundant memory cell 10 repairs a defective memory cell, there is a one-to-one mapping relationship, that is, each redundant memory cell 10 can only repair at most one defective memory cell. Therefore, by indicating the occupation information of the redundant memory cell 10, it is convenient to find the redundant memory cell 10 that is not occupied yet in the repair process. For example, if a redundant memory cell 10 is already used to repair a defective memory cell, the occupation information of the redundant memory cell 10 is occupied, and the corresponding status signal may be 0.

Further, the normal memory cell and the redundant memory cell 10 are simultaneously prepared, i.e., the redundant memory cell 10 has the same hardware structure as the normal memory cell. Also, since the probability of occurrence of defective memory cells is low, only a small number of redundant memory cells 10 are generally provided in the memory. Also, the number of the redundant memory cells 10 is proportional to the number of the normal memory cells and inversely proportional to the yield of the manufacturing process. That is, the greater the number of normal memory cells, the lower the yield of the manufacturing process, and accordingly, the more redundant memory cells 10 need to be provided.

And the repair module 20 is respectively connected to the plurality of redundant memory cells 10, and is configured to determine a target memory cell from the plurality of redundant memory cells 10 according to the plurality of status signals, and repair a defective memory cell through the target memory cell. Further, the repair module 20 can repair different defective memory cells in a plurality of repair stages, respectively, and the plurality of repair stages share the plurality of redundant memory cells 10. In the existing memory, a corresponding redundant memory cell 10 is usually set for each repair stage, that is, each redundant memory cell 10 can only be used in the set repair stage, however, this use method may result in insufficient utilization rate of the redundant memory cell 10, and thus, insufficient repair rate of the defective memory cell.

For example, if the memory is configured with two repair stages, namely a first repair stage and a second repair stage, one defective memory cell needs to be repaired in the first repair stage, and three defective memory cells need to be repaired in the second repair stage. If the existing repair method is adopted and each repair stage is correspondingly provided with two redundant memory cells 10, only two defective memory cells can be repaired in the second repair stage, that is, the defective memory cells cannot be completely repaired. If the mode that a plurality of redundant memory cells 10 are shared in a plurality of repair stages and four redundant memory cells 10 are arranged in total in the embodiment of the application is adopted, all the defective memory cells can be repaired, so that the repair rate and the repair flexibility of the defective memory cells are improved, a repair circuit with higher repair flexibility and reliability is provided, and the read-write accuracy of the memory is further improved.

In this embodiment, the repair circuit includes: a plurality of redundant memory cells 10, each of the redundant memory cells 10 configured with a status signal; a repair module 20, respectively connected to the plurality of redundant memory cells 10, configured to determine a target memory cell from the plurality of redundant memory cells 10 according to the plurality of status signals, and repair a defective memory cell through the target memory cell; the target memory cells correspond to the defective memory cells one to one, the repair module 20 can repair different defective memory cells in a plurality of repair stages, and the plurality of repair stages share the plurality of redundant memory cells 10. By selecting a target memory cell in response to a status signal of the redundant memory cell 10 and sharing the redundant memory cell 10 at a plurality of repair stages, the repair rate and the repair flexibility of the defective memory cell are improved, i.e., a repair circuit having higher repair flexibility and reliability is provided.

Further, the plurality of repair stages includes a first repair stage and a second repair stage, and the memory repair unit 200 includes a first repair unit 210 and a second repair unit. The first repair unit 210 is respectively connected to the selection unit 100 and the plurality of redundant memory cells 10, and is configured to repair the defective memory cells in the first repair stage; second repair units are respectively connected to the selection unit 100 and the plurality of redundant memory cells 10, and are used for repairing the defective memory cells in the second repair stage. Wherein the first repair phase is earlier than the second repair phase, and the first repair unit 210 occupies the redundant memory cell 10 in preference to the second repair unit. Still further, the first repair stage is a post-package repair stage, and the second repair stage is a self-repair stage. It can be understood that, according to the repair requirement, three or more repair stages can be set, and a greater number of repair units are correspondingly set, so as to correspond to different repair stages one by one, thereby providing more accurate and comprehensive repair, and further improving the reliability and stability of the memory.

Fig. 2 is a schematic structural diagram of a repair circuit of a second embodiment, and referring to fig. 2, in this embodiment, the repair circuit includes a repair module 20 and a plurality of redundant memory cells 10, where the repair module 20 includes a selection unit 100 and a memory repair unit 200.

A selection unit 100 for generating a unit selection signal according to a plurality of said state signals. Specifically, the selection unit 100 may be a digital logic circuit, that is, the selection unit 100 may include a plurality of logic gates that perform a logic operation according to an input state signal, thereby generating a unit selection signal. The number of the status signals is the same as the number of the redundant memory cells 10, and the status signals correspond to the redundant memory cells. Illustratively, if four redundant memory cells 10 are provided, the selection unit 100 receives 4 status signals and performs a logic operation on the 4 status signals.

And a memory repair unit 200, respectively connected to the selection unit 100 and the plurality of redundant memory cells 10, for receiving the cell selection signal, determining the target memory cell according to the cell selection signal, and repairing the defective memory cell through the target memory cell.

In some embodiments, the cell selection signal may include only one signal, but the signal may output multi-bit data in series, and the memory repair unit 200 may determine an unoccupied redundant memory cell 10 according to the received multi-bit data, thereby repairing the defective memory cell. Illustratively, taking the repair circuit including four redundant memory cells 10 as an example, the cell selection signal may include two bits of data, and if the cell selection signal is "00", the first redundant memory cell 11 is selected; if the cell selection signal is "01", the second redundant memory cell 12 is selected; if the cell selection signal is "10", the third redundant memory cell 13 is selected; if the cell selection signal is "11", the fourth redundant memory cell 14 is selected. The signal transmission mode of serially outputting the multi-bit data has the advantages of simpler required hardware structure and fewer devices, so the signal transmission mode is more suitable for the memory with small volume and lower requirement on data reading and writing speed.

In other embodiments, the cell selection signal includes a plurality of enable signals, the enable signals correspond to the redundant memory cells 10 one to one, and at most one of the enable signals is enabled at the same time; the selection unit 100 includes a plurality of generation circuits 110, and each of the generation circuits 110 is configured to generate one of the enable signals. Wherein the memory repair unit 200 is configured to determine the redundant memory cell 10 corresponding to the enable signal with valid enable as the target memory cell. Illustratively, taking the repair circuit including four redundant memory cells 10 as an example, when the enable signal is in a high level state, the enable signal is enabled, and if the enable signals include three low level signals and one high level signal, the redundant memory cell 10 corresponding to the high level signal is selected as the target memory cell to repair the defective memory cell. In this embodiment, a mode of synchronously calculating and transmitting a plurality of signals is adopted, and the operating speed is higher, so that the method is more suitable for a memory with a large number of memory cells, a large data volume and a higher requirement on data reading and writing speed.

Further, the selection unit 100 is configured to generate the unit selection signal according to a preset repair order and a plurality of the status signals. Wherein, the redundant memory cell 10 in the first repair order is defined as the first redundant memory cell 11, the redundant memory cell 10 in the second repair order is defined as the second redundant memory cell 12, and so on. According to the preset repair sequence, when at least one of all the redundant memory repair units 200 in the repair sequence before the nth redundant memory unit 10 is unoccupied, the nth enable signal is disabled; when all the redundant memory repair units 200 located before the nth redundant memory unit 10 in the repair order are occupied and the nth redundant memory unit 10 is not occupied, the nth enable signal is enabled. For example, when the first redundant memory cell 11 or the second redundant memory cell 12 is not occupied, the third enable signal corresponding to the third redundant memory cell 13 is disabled; when the first redundant memory cell 11 and the second redundant memory cell 12 are both occupied and the third redundant memory cell 13 is not occupied, the corresponding third enable signal is enabled.

Still further, the above-mentioned purpose of selecting the redundant repair unit according to the repair order can be achieved by the circuit structure inside the selection unit 100, that is, the repair circuit of the present embodiment can select the appropriate redundant repair unit for repair without an external control signal. Specifically, fig. 3 is a schematic structural diagram of a repair circuit of a third embodiment, and referring to fig. 3, in this embodiment, the selection unit 100 includes a first generation circuit 111, and the first generation circuit 111 is configured to generate a first enable signal. Wherein, when the first redundant memory cell 11 is occupied, the first enable signal is disabled; the first enable signal is active when the first redundant memory cell 11 is not occupied. For example, if the first state signal is high, indicating that the first redundant memory cell 11 is not occupied, and the first enable signal is high and active, the level state of the first enable signal can be made to follow the level state of the first state signal, that is, the signal output by the first generation circuit 111 is the same as the input signal. Therefore, the output function can be realized with a simple hardware configuration without providing an additional logic gate in the first generation circuit 111.

With continuing reference to fig. 3, in the present embodiment, the selection unit 100 further includes an nth generation circuit 110, where n is an integer greater than 1, and exemplarily, in the embodiment of fig. 3, the selection unit 100 further includes a second generation circuit 112, a third generation circuit 113, and a fourth generation circuit 114, where the nth generation circuit 110 is configured to generate an nth enable signal, that is, the nth enable signal corresponds to the nth generation circuit 110 in a one-to-one manner. Fig. 4 is a schematic structural diagram of a repair circuit of a fourth embodiment, and referring to fig. 4, in this embodiment, the nth generation circuit 110 includes a second logic gate 1102 and n-1 first logic gates 1101.

The n-1 first logic gates 1101 are configured to receive the n-1 state signals in a one-to-one correspondence, and perform logic calculation on the received state signals, where the n-1 state signals are the first state signal to the n-1 state signal, respectively. Further, the first logic gate 1101 may be a not gate. Illustratively, taking the fourth generating circuit 114 as an example, the fourth generating circuit 114 includes 3 first logic gates 1101, and the 3 first logic gates 1101 are respectively configured to receive the first state signal, the second state signal and the third state signal in a one-to-one correspondence, the 3 first logic gates 1101 are all not gates, and the three first logic gates 1101 are respectively configured to output the inverted first state signal, the inverted second state signal and the inverted third state signal in a one-to-one correspondence.

A second logic gate 1102, where the second logic gate 1102 is configured with n input ends and one output end, n-1 of the input ends are respectively connected to the output ends of n-1 of the first logic gates 1101 in a one-to-one correspondence manner, the remaining input ends are used to receive an nth state signal, and the second logic gate 1102 is used to perform a logic calculation on a plurality of input signals to generate the nth enable signal. Further, the second logic gate 1102 may be an and gate. As described above, the second logic gate 1102 in the fourth generating circuit 114 is configured with 4 input terminals, 3 of which are respectively configured to receive the inverted first state signal, the inverted second state signal and the inverted third state signal in a one-to-one correspondence, and the remaining one input terminal is configured to receive the fourth state signal, and the second logic gate 1102 performs a logical and operation on the input signals to generate the fourth enable signal.

It is to be understood that the first logic gate 1101 of the embodiment of the present application is not limited to a not gate, and the second logic gate 1102 is not limited to an and gate. For example, a not gate may be provided in the first generation circuit 111, the second logic gate 1102 may be provided as a nand gate, and the memory repair unit may be controlled to select the redundant memory cell 10 corresponding to the enable signal in the low level state, so as to repair the defective memory cell as the target memory cell. Therefore, a circuit configuration that can realize selection and repair according to a preset repair order based on a plurality of enable signals output by the selection unit 100 is within the scope of the present application and is not limited to the configuration of the selection unit 100 in the foregoing embodiments.

In one embodiment, at least a portion of the first logic gate 1101 is shared by a plurality of the generating circuits 110. Specifically, fig. 5 is a schematic structural diagram of a repair circuit of a fifth embodiment, and in the present embodiment, in combination with fig. 4 and 5, a plurality of logic gates for realizing the same function may be shared. Illustratively, referring to fig. 4, the second generating circuit 112, the third generating circuit 113 and the fourth generating circuit 114 all need to receive the inverted first state signal, accordingly, each generating circuit 110 of the embodiment of fig. 4 is provided with a not gate, and each not gate receives the first state signal independently and performs the inversion operation. In the embodiment shown in fig. 5, the first state signal is inverted and the inverted signal is transmitted to each of the second logic gates 1102. That is, compared with the embodiment of fig. 4, the embodiment of fig. 5 achieves the same technical effect by using fewer logic devices, so that a repair circuit with a simpler structure is provided, and the integration level of the memory can be effectively improved. It will be appreciated that in other embodiments, only some of the logic gates for performing the same function may be shared, and some of the logic gates may not be shared.

Fig. 6 is a schematic structural diagram of a repair circuit according to a sixth embodiment, and referring to fig. 6, in this embodiment, the selection unit 100 is further configured to receive an externally input repair phase signal and output a unit selection signal according to the repair phase signal. Specifically, if the state signal is at a high level, it indicates that the corresponding redundant memory cell 10 is unoccupied, and if the enable signal in the cell selection signal is at a high level, it indicates that the corresponding redundant memory cell 10 is selected for repair. In this embodiment, if at least two redundant memory cells 10 need to be reserved for the second repair stage, the repair stage signal can be controlled to be always at a low level in the first repair stage, and after the selection unit 100 calculates, the third enable signal and the fourth enable signal are always at a low level, that is, the third redundant memory cell 13 and the fourth redundant memory cell 14 cannot be occupied in the first repair stage, so that the purpose of reserving a part of the redundant memory cells 10 can be achieved, and a more flexible repair circuit is implemented. In this embodiment, for example, if only one redundant memory cell 10 is used in the first repair stage, for example, only the first redundant memory cell 11 is used, then three redundant memory cells 10 may be available in the second repair stage, for example, the second redundant memory cell 12, the second redundant memory cell 13, and the second redundant memory cell 14 may be available, which is equivalent to the first repair stage and the second repair stage sharing the first redundant memory cell 11, the second redundant memory cell 12, the second redundant memory cell 13, and the second redundant memory cell 14, thereby implementing a more flexible repair circuit.

In one embodiment, the repair circuit may further include a detection module 30 connected to the plurality of normal memory cells, where the detection module 30 is configured to detect an operating status of the plurality of normal memory cells and determine the defective memory cell from the plurality of normal memory cells according to the operating status.

Specifically, the detection module 30 is connected with the normal memory cells to test the connected normal memory cells in the test mode. That is, when the memory is in the test mode, the detection module 30 performs the corresponding test function. The memory switches to a test mode in response to a test trigger signal. For example, the memory may automatically generate a test trigger signal to switch to the test mode each time the memory is powered up. The memory may also be switched to the test mode in response to an externally input test trigger signal, which may be, for example, a signal input by a user through an electronic device connected to the memory. The memory can also respond to a test trigger signal output by a built-in controller to switch to a test mode, and the controller can output one test trigger signal after the memory runs for preset time every time so as to realize regular monitoring on the normal memory unit. It will be appreciated that responsive defect tests may be set for each repair phase, and that different test trigger signals may be set at different repair phases to allow detection module 30 to accurately distinguish between different repair phases.

The defect test may be performed by the detection module 30 responding to the test trigger signal to automatically generate one or more test data, and writing the test data into each memory cell to be tested, and after a certain time, reading data from the memory cell, and comparing the read data with the automatically generated test data to determine whether the memory function of the memory cell is normal, where if the read data and the written data of a memory cell are different, the memory cell is a defective memory cell.

An embodiment of the present application further provides a memory, including: the memory comprises a repair circuit and a plurality of normal memory units, wherein the repair circuit is respectively connected with the normal memory units; wherein the normal memory cell with abnormal operation state is used as the defect memory cell. It can be understood that, for the specific structure of the repair circuit of this embodiment, reference may be made to the foregoing embodiment, and details are not described again in this embodiment. The embodiment realizes a memory with higher reliability and flexibility based on a repair circuit with a flexible repair function.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express a few embodiments of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the concept of the embodiments of the present application, and these embodiments are within the scope of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the appended claims.

Claims (13)

1. A repair circuit, comprising:

a plurality of redundant memory cells, each of the redundant memory cells configured with a status signal;

the repair module is respectively connected with the plurality of redundant storage units and is used for determining a target storage unit from the plurality of redundant storage units according to the plurality of state signals and repairing a defective storage unit through the target storage unit;

the target memory cells correspond to the defective memory cells one to one, the repair module can repair different defective memory cells in a plurality of repair stages respectively, and the repair stages share the redundant memory cells.

2. The repair circuit of claim 1, wherein the repair module comprises:

a selection unit for generating a unit selection signal according to the plurality of status signals;

and the storage repairing unit is respectively connected with the selection unit and the plurality of redundant storage units, and is used for receiving the unit selection signal, determining the target storage unit according to the unit selection signal, and repairing the defective storage unit through the target storage unit.

3. The repair circuit of claim 2, wherein the selection unit is configured to generate the cell selection signal according to a preset repair order and a plurality of the status signals.

4. The repair circuit of claim 3, wherein the cell selection signal comprises a plurality of enable signals, the plurality of enable signals corresponding to the plurality of redundant memory cells one-to-one, and at most one of the plurality of enable signals being asserted at a same time;

the selection unit comprises a plurality of generating circuits, and each generating circuit is used for correspondingly generating one enabling signal;

the storage repair unit is used for determining the redundant storage unit corresponding to the enable signal with valid enable as the target storage unit.

5. The repair circuit according to claim 4, wherein the status signal carries occupation information of the corresponding redundant memory cell, the occupation information including occupied and unoccupied, the selection unit comprises a first generation circuit for generating a first enable signal, the redundant memory cells in a first repair order are defined as first redundant memory cells; wherein the content of the first and second substances,

when the first redundant memory cell is occupied, the first enabling signal is disabled; the first enable signal is active when the first redundant memory cell is not occupied.

6. The repair circuit of claim 4, wherein the redundant memory cells in the nth repair order are defined as nth redundant memory cells, n being a positive integer greater than 1, the selection unit further comprising an nth generation circuit for generating an nth enable signal; wherein the content of the first and second substances,

when at least one of all the redundant storage repair units in the repair sequence before the nth redundant storage unit is unoccupied, enabling the nth enable signal to be invalid; and when all the redundant storage repair units in the repair sequence before the nth redundant storage unit are occupied and the nth redundant storage unit is not occupied, enabling the nth enable signal to be effective.

7. The repair circuit of claim 6, wherein the nth generation circuit comprises:

n-1 first logic gates, wherein the n-1 first logic gates are used for receiving the n-1 state signals in a one-to-one correspondence manner and carrying out logic calculation on the received state signals;

the second logic gate is provided with n input ends and an output end, the n-1 input ends are respectively connected with the output ends of the n-1 first logic gates in a one-to-one correspondence mode, the rest input ends are used for receiving nth state signals, and the second logic gate is used for carrying out logic calculation on a plurality of input signals so as to generate the nth enable signal.

8. The repair circuit of claim 7, wherein the first logic gate is a not gate and the second logic gate is an and gate.

9. The repair circuit of claim 7, wherein a plurality of the generation circuits share at least a portion of the first logic gate.

10. The repair circuit of claim 2, wherein the plurality of repair phases includes a first repair phase and a second repair phase, the memory repair cell comprising:

the first repair unit is respectively connected with the selection unit and the plurality of redundant memory units and is used for repairing the defective memory unit in the first repair stage;

the second repair unit is respectively connected with the selection unit and the plurality of redundant memory units and is used for repairing the defective memory unit in the second repair stage;

wherein the first repair phase is earlier than the second repair phase, and the first repair unit occupies the redundant memory cell in preference to the second repair unit.

11. The repair circuit of claim 10, wherein the first repair phase is a post-package repair phase and the second repair phase is a self-repair phase.

12. The repair circuit of claim 1, further comprising:

the detection module is used for detecting the operating states of the normal storage units and determining the defective storage unit from the normal storage units according to the operating states.

13. A memory, comprising:

a plurality of normal memory cells;

the repair circuit according to any one of claims 1 to 12, which is connected to a plurality of the normal memory cells, respectively;

wherein the normal memory cell with abnormal operation state is used as the defect memory cell.

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