CN111984478A - EEPROM chip transfer type test method and system - Google Patents
EEPROM chip transfer type test method and system Download PDFInfo
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- CN111984478A CN111984478A CN202010708698.8A CN202010708698A CN111984478A CN 111984478 A CN111984478 A CN 111984478A CN 202010708698 A CN202010708698 A CN 202010708698A CN 111984478 A CN111984478 A CN 111984478A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
Abstract
The invention discloses a transmission type test method of an EEPROM chip, which is characterized in that n chips are tested in parallel once, the first chip is written and read after the data source is read, the read data is written into the next chip by a test machine and read out, the data is transmitted for n-1 times in total by analogy, and then the data read out from the nth chip is compared with the source data given by a PC machine. If the comparison results are consistent, all the n tested chips have normal functions, and the comparison is only needed once, while the comparison times of the test method in the prior art are the same as the number of the tested chips and need to be compared for n times; if the comparison result is inconsistent, comparing the data of the first n-1 tested chips with the source data for n-2 times, and finding out all defective products, wherein the probability of inconsistent comparison in the existing test process is very small. The invention also discloses a transmission type test system of the EEPROM chip. The invention shortens the time of testing the read-write function of the EPPROM by the tester and the time of data comparison, and greatly improves the testing efficiency.
Description
Technical Field
The invention belongs to the technical field of chip testing, and particularly relates to a transmission type testing method and system for an EEPROM chip.
Background
The existing EPPROM chip function test method comprises the following steps: the number of single parallel test pieces is set as N (N is more than or equal to 1 and less than or equal to 16, N belongs to N +), N EPPROM full addresses are written and read firstly, the read EPPROM data are compared with the source data given by a PC (personal computer), the performance of the chip is judged, N EPPROMs are tested, the number of comparison with the source data given by the PC is N-1, the larger N is, the longer the time of logic operation and Boolean operation is, the longer the test time of the test method is, the test efficiency is low, and the more resources of the test machine are occupied.
Disclosure of Invention
The technical problems solved by the invention are as follows: the existing testing method has long testing time, low testing efficiency and more occupied resources of a testing machine.
The technical scheme is as follows: in order to solve the technical problems, the technical scheme adopted by the invention is as follows:
the invention discloses a transmission type test method of an EEPROM chip, which is characterized in that n chips are tested in parallel once, the first chip is written and read after the data source is read, the read data is written into the next chip by a test machine and read out, the data is transmitted for n-1 times in total by analogy, and then the data read out from the nth chip is compared with the source data given by a PC machine.
Preferably, if the data read from the nth chip is consistent with the source data given by the PC, all the nth chips are qualified products; if the data read from the nth chip is inconsistent with the source data given by the PC, a defective product exists.
Preferably, when defective products occur, the data read by each chip is compared with the source data one by one.
Preferably, the number of comparisons is 1 if the data read from the nth chip matches the source data given by the PC, and n-1 if a defective product is present.
Preferably, the data read from each chip is stored in a tester for data comparison when a defective product is present.
Preferably, the number of chips tested in parallel in a single time is more than or equal to 1 and less than or equal to 16, and N is equal to N.
The invention also discloses a system for realizing the EEPROM chip transfer type test method, which comprises a master controller PC, a vector-based PXI digital channel board card, a power supply unit and a tested chip, wherein the master controller PC is connected with the tested chip through the vector-based PXI digital channel board card, and the power supply unit is connected with the tested chip to supply power to the tested chip.
Preferably, a field effect transistor is arranged between the power supply unit and the tested chip, the vector-based PXI digital channel board card is connected with the field effect transistor, and the vector-based PXI digital channel board card controls the power-off and power-on of the tested chip through the field effect transistor.
Preferably, during testing, the vector-based PXI digital channel board card controls the field effect transistor to be conducted, the power supply unit applies standard voltage to the tested chip, the controller PC sends clear data to clear the tested chip through the vector-based PXI digital channel board card, the controller PC sends test source data to the tested chip DUT1 through the vector-based PXI digital channel board card, the vector-based PXI digital channel board card controls the field effect transistor MOSFET1 after sending is finished, the DUT1 is powered off and then on again, the DUT1 data is read out and stored, read values are written into the next DUT. If the data of the first n-1 DUTs are inconsistent with the source data, the data of the first n-1 DUTs are compared with the source data for n-2 times, and all defective products are found out.
Has the advantages that: compared with the prior art, the invention has the following advantages:
the invention relates to a transmission type test method of an EEPROM chip, which adopts a data transmission mode, wherein data read from a tested chip is not compared with source data one by one, but is stored in a test machine, and is written into a next tested chip as the source data of the next chip until the data is transmitted to the last chip, the data read from the last chip is compared with the source data given by a main controller PC, if the comparison result is consistent, all n tested chips have normal functions, and only one comparison is needed at the moment, while the comparison times of the test method in the prior art are the same as the number of the test chips and need n comparisons; if the comparison result is inconsistent, comparing the data of the first n-1 tested chips with the source data for n-2 times, and finding out all defective products, wherein the probability of inconsistent comparison in the existing test process is very small. Therefore, the invention shortens the time for testing the read-write function of the EPPROM by the tester and the time for comparing data, and greatly improves the testing efficiency.
Drawings
FIG. 1 is a schematic diagram of a method and system for transitive testing of EEPROM chips.
Detailed Description
The present invention will be further illustrated by the following specific examples, which are carried out on the premise of the technical scheme of the present invention, and it should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention.
The invention discloses a transmission type test method of an EEPROM chip, which is characterized in that n chips are tested in parallel once, the first chip is written and read after the data source is read, the read data is written into the next chip by a test machine and read out, the data is transmitted for n-1 times in total by analogy, and then the data read out from the nth chip is compared with the source data given by a PC machine. If the data read from the nth chip is consistent with the source data given by the PC, all the n chips are qualified products, and the comparison frequency is only 1 time; if the data read from the nth chip is inconsistent with the source data given by the PC, a defective product exists. When defective products appear, the data read by each chip is compared with the source data one by one, the comparison frequency is n-1, and the probability that the chips are purely in the defective chips is small, so that the probability that the total comparison frequency is (1+ (n-1)) is very small.
In order to ensure the testing efficiency, the number of chips tested in parallel in one time is more than or equal to 1 and less than or equal to 16, and N belongs to N.
And data comparison is conveniently carried out when defective products appear. The data read from each chip is stored in the tester, for example, the data read from the 1 st chip is DUT1, DUT1 is stored in the tester, DUT1 is written to the 2 nd chip, the data read from the second chip is DUT2, DUT2 is stored in the tester, and so on, the data stored in the tester is 16 groups of data, DUT1-DUT 16.
The inventionThe system comprises a master controller PC, a vector-based PXI digital channel board card (namely a testing machine), a power supply unit and a tested chip, wherein the master controller PC is connected with the tested chip through the vector-based PXI digital channel board card, and the power supply unit is connected with the tested chip to supply power to the tested chip. The master controller PC adopts NI PXIe-8880, the vector-based PXI digital channel board card adopts NI PXIe-6570, and the DUT1～DUT16Data is stored in LVM (large vector memory) of NI PXIe-6570, the LVM is 128MB, and the DUT monolithic maximum 256KB, thus fully meeting the test requirements; the power supply unit adopts NI PXIe-4113,
a P-channel trench field effect transistor MOSFET is arranged between the power supply unit and each tested chip, the MOSFET adopts IRFHS9301PBF, the vector-based PXI digital channel board card is connected with the field effect transistor, and the vector-based PXI digital channel board card can randomly control the power-off and power-on of the tested chip through the intermediate medium field effect transistor.
During testing, the vector-based PXI digital channel board NI PXIe-6570 controls the MOSFET to be conducted, the power supply unit NI PXIe-4113 applies standard voltage to a tested chip, the controller PC sends zero clearing data to clear the tested chip through the vector-based PXI digital channel board NI PXIe-6570, the controller PC sends test source data to the tested chip DUT1 through the vector-based PXI digital channel board NI PXIe-6570, the vector-based PXI digital channel board card controls the MOSFET1 after sending is finished, the DUT1 loses power and is electrified again, the DUT1 data is read out for storage, read values are written into the next DUT n until the DUT n data is read out and stored, whether the DUT n data is consistent with the source data or not is compared, and if the DUT n functions are normal; if the data of the first n-1 DUTs are inconsistent with the source data, the data of the first n-1 DUTs are compared with the source data for n-1 times, and all defective products are found out, wherein the defective products are small-probability events.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that it is obvious to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and these modifications and improvements should also be considered as the protection scope of the present invention.
Claims (9)
1. A transmission type test method of an EEPROM chip is characterized in that: and testing n chips in parallel at a time, writing and reading the data source of the first chip first, writing the read data into the next chip by the tester and reading the data, repeating the steps until the data is transferred for n-1 times totally, and comparing the data read from the nth chip with the source data given by the PC.
2. The EEPROM chip transfer type test method of claim 1, wherein: if the data read from the nth chip is consistent with the source data given by the PC, all the nth chips are qualified products; if the data read from the nth chip is inconsistent with the source data given by the PC, a defective product exists.
3. The EEPROM chip transfer type test method of claim 2, wherein: and when defective products appear, comparing the data read out by each chip with the source data one by one.
4. The EEPROM chip transfer type test method of claim 3, wherein: if the data read from the nth chip is consistent with the source data given by the PC, the comparison frequency is 1, and if a defective product appears, the comparison frequency is n-1.
5. The EEPROM chip transfer type test method of claim 1, wherein: the data read from each chip is stored in a tester for data comparison when a defective product appears.
6. The EEPROM chip transfer type test method of claim 1, wherein: the number of chips tested in parallel in a single time is more than or equal to 1 and less than or equal to 16, and N belongs to N.
7. A system for realizing the EEPROM chip transfer type test method of any one of claims 1 to 6, which is characterized in that: the device comprises a master controller PC, a vector-based PXI digital channel board card, a power supply unit and a tested chip, wherein the master controller PC is connected with the tested chip through the vector-based PXI digital channel board card, and the power supply unit is connected with the tested chip to supply power to the tested chip.
8. The EEPROM chip pass-through test system of claim 7, wherein: a field effect tube is arranged between the power supply unit and the tested chip, the vector-based PXI digital channel board card is connected with the field effect tube, and the vector-based PXI digital channel board card controls the power-off and power-on of the tested chip through the field effect tube.
9. The EEPROM chip pass-through test system of claim 1, wherein: during testing, the vector-based PXI digital channel board card controls the field effect transistor to be conducted, the power supply unit applies standard voltage to a tested chip, the controller PC sends clear data to clear the tested chip through the vector-based PXI digital channel board card, the controller PC sends test source data to the tested chip DUT1 through the vector-based PXI digital channel board card, the vector-based PXI digital channel board card controls the field effect transistor MOSFET1 after sending is finished, the DUT1 is powered off and then powered on again, the DUT1 data is read out and stored, read values are written into the next DUT … until the DUT n data is read out and stored, whether the DUT n data is consistent with the source data is compared, and if yes, the n DUTs have normal functions; if the data of the first n-1 DUTs are inconsistent with the source data, the data of the first n-1 DUTs are compared with the source data for n-2 times, and all defective products are found out.
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| CN202010708698.8A CN111984478A (en) | 2020-07-21 | 2020-07-21 | EEPROM chip transfer type test method and system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114255155A (en) * | 2022-02-24 | 2022-03-29 | 荣耀终端有限公司 | Graphics processor testing method and electronic equipment |
Citations (6)
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| EP0385591A2 (en) * | 1989-02-28 | 1990-09-05 | Nortel Networks Corporation | Serial testing technique for embedded memories |
| KR20000060189A (en) * | 1999-03-12 | 2000-10-16 | 윤종용 | A parallel test system of a semiconductor memory device |
| KR20030054198A (en) * | 2001-12-24 | 2003-07-02 | 삼성전자주식회사 | Built-in self-test circuit for testing multiple embedded memory devices and integrated circuit including the same |
| CN105185415A (en) * | 2015-10-28 | 2015-12-23 | 上海斐讯数据通信技术有限公司 | Method and device for testing EEPROM of I2C |
| CN110021334A (en) * | 2019-04-19 | 2019-07-16 | 上海华虹宏力半导体制造有限公司 | A kind of crystal round test approach |
| CN110287073A (en) * | 2019-06-27 | 2019-09-27 | 中国兵器工业集团第二一四研究所苏州研发中心 | A kind of test device and method for a variety of multiple asynchronous serial communication peripheral hardwares |
-
2020
- 2020-07-21 CN CN202010708698.8A patent/CN111984478A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0385591A2 (en) * | 1989-02-28 | 1990-09-05 | Nortel Networks Corporation | Serial testing technique for embedded memories |
| KR20000060189A (en) * | 1999-03-12 | 2000-10-16 | 윤종용 | A parallel test system of a semiconductor memory device |
| KR20030054198A (en) * | 2001-12-24 | 2003-07-02 | 삼성전자주식회사 | Built-in self-test circuit for testing multiple embedded memory devices and integrated circuit including the same |
| CN105185415A (en) * | 2015-10-28 | 2015-12-23 | 上海斐讯数据通信技术有限公司 | Method and device for testing EEPROM of I2C |
| CN110021334A (en) * | 2019-04-19 | 2019-07-16 | 上海华虹宏力半导体制造有限公司 | A kind of crystal round test approach |
| CN110287073A (en) * | 2019-06-27 | 2019-09-27 | 中国兵器工业集团第二一四研究所苏州研发中心 | A kind of test device and method for a variety of multiple asynchronous serial communication peripheral hardwares |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114255155A (en) * | 2022-02-24 | 2022-03-29 | 荣耀终端有限公司 | Graphics processor testing method and electronic equipment |
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