CN105761759A - Test method and test device for random access memory - Google Patents
Test method and test device for random access memory Download PDFInfo
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- CN105761759A CN105761759A CN201610072807.5A CN201610072807A CN105761759A CN 105761759 A CN105761759 A CN 105761759A CN 201610072807 A CN201610072807 A CN 201610072807A CN 105761759 A CN105761759 A CN 105761759A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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Abstract
The invention is applicable to the technical field of tests, and discloses a test method and a test device for an RAM (Random Access Memory). The test method comprises the following steps: writing first data in all addresses of the RAM according to a first address order; executing the following steps on each address of the RAM in turn according to a second address order: checking the first data of the address, and writing second data in the address, wherein an XOR result of the first data and the second data is 1; executing the following steps on each address of the RAM in turn according to a third address order: checking the second data of the address, and writing the first data in the address; executing the following step on each address of the RAM in turn according to a fourth address order: checking the first data of the address. According to the invention, test time is shortened as much as possible provided that a fault-coverage rate is ensured.
Description
Technical field
The invention belongs to technical field of measurement and test, particularly relate to method of testing and the device of random access memory (RandomAccessMemory, RAM).
Background technology
Along with the development of digital circuit, RAM, especially dynamic random access memory (DynamicRandomAccessMemory, DRAM) processing procedure is more and more less, integrated level is more and more higher, and the arrangement of memory element is more tight, adds that memorizer has high complexity and more shared signal, run under high speed signal environment, easily producing various types of faults, therefore, RAM is after packaging is accomplished, needing through strict test, test just can be fed to client by rear.
The core of ram test is testing algorithm, existing testing algorithm includes marching test algorithm, sweep test algorithm, checkerboard pattern testing algorithm, diagonal test algorithm etc., there is testing time longer technological deficiency in existing algorithm, thus extending the test period of RAM.
Summary of the invention
In view of this, embodiments provide method of testing and the device of RAM, longer to solve the prior art testing time, cause the problem that the test period of RAM extends.
First aspect, it is provided that the method for testing of a kind of RAM, including:
The first data are write to all addresses of RAM according to the first sequence of addresses；
According to the second sequence of addresses, perform successively to all addresses of described RAM: verify described first data of this address, this address backward write the second data, the XOR result of described first data and described second data is 1；
According to the 3rd sequence of addresses, perform successively to all addresses of described RAM: verify described second data of this address, this address backward write the first data；
According to the 4th sequence of addresses, perform successively to all addresses of described RAM: verify described first data of this address.
Second aspect, it is provided that the test device of a kind of RAM, including:
First test cell, for writing the first data according to the first sequence of addresses to all addresses of RAM；
Second test cell, for according to the second sequence of addresses, performs to all addresses of described RAM: verify described first data of this address successively, this address backward write the second data, the XOR result of described first data and described second data is 1；
3rd test cell, for according to the 3rd sequence of addresses, performs to all addresses of described RAM: verify described second data of this address successively, this address backward write the first data；
4th test cell, for according to the 4th sequence of addresses, performing successively to all addresses of described RAM: verify described first data of this address.
By the verification operation mentioned in the embodiment of the present invention, the charge status of bit address each in RAM can be tested, to judge whether RAM can correctly carry out discharge and recharge according to the content of read-write operation, this test content covers the various fault models of RAM, and under the premise having ensured fault coverage, shorten the testing time as much as possible.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme in the embodiment of the present invention, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the flowchart of the method for testing of the RAM that the embodiment of the present invention provides；
Fig. 2 be the embodiment of the present invention provide RAM method of testing realize exemplary plot；
Fig. 3 is the structured flowchart of the test device of the RAM that the embodiment of the present invention provides.
Detailed description of the invention
In being described below, in order to illustrate rather than in order to limit, it is proposed that the such as detail of particular system structure, technology etc, in order to thoroughly cut and understand the embodiment of the present invention.But, it will be clear to one skilled in the art that and can also realize the present invention in the other embodiments do not have these details.In other situation, omit the detailed description to well-known system, device, circuit and method, in order to avoid unnecessary details hinders description of the invention.
What Fig. 1 illustrated the method for testing of the RAM that the embodiment of the present invention provides realizes flow process, and details are as follows:
In S101, write the first data according to the first sequence of addresses to all addresses of RAM.
In S102, according to the second sequence of addresses, perform successively to all addresses of described RAM: verify described first data of this address, this address backward write the second data, the XOR result of described first data and described second data is 1.
In S103, according to the 3rd sequence of addresses, perform successively to all addresses of described RAM: verify described second data of this address, this address backward write the first data.
In S104, according to the 4th sequence of addresses, perform successively to all addresses of described RAM: verify described first data of this address.
In the test process to RAM shown in Fig. 1, altogether need each in all addresses of RAM is carried out respectively the read-write operation of six times, the various charge status of each address can be tested and verify by these six read-write operations, wherein, charge status includes: drawn as high level (when bit address is currently for " 0 " write " 1 ") by bit address by low level, and bit address is drawn as low level (when bit address is currently for " 1 " write " 0 ") by high level, therefore, in embodiments of the present invention, the XOR result of described first data and described second data is 1, when the length of the first data and the second data is one, first data are " 0 " and the second data are " 1 ", or the first data are " 1 " and the second data are " 0 ".
As a kind of implementation the most basic, the embodiment shown in Fig. 1 can realize with position for operating unit, i.e. read-write operation is all that a position in RAM is written and read every time.nullAnd according to the operation principle of memory element，RAM can be divided into static RAM (StaticRAM，And dynamic random access memory (DynamicRAM SRAM)，DRAM)，For DRAM，Usually byte (8)、The organizational structure of word (16) or double word (32)，Processor is when carrying out data access to DRAM，It is all according to byte、The mode of word or double word performs read-write operation each time，Therefore，Difference according to DRAM organizational structure，The length of the first data and the second data is also different，When the DRAM organizational structure being bytewise，The length of the first data and the second data is 8，When the DRAM organizational structure being font formula，The length of the first data and the second data is 16，When the DRAM organizational structure being double word form，The length of the first data and the second data is 32.Organizational structure for bytewise, when the first data respectively " 00000000 " or " 01010101 " or " 00110011 " or " 00001111 ", corresponding the second data respectively " 11111111 " or " 10101010 " or " 11001100 " or " 11110000 ".
In embodiments of the present invention, described sequence of addresses, for representing in each step of S101～S104, memory space in RAM is written and read the order of operation, in embodiments of the present invention, need to ensure in sequence of addresses that the data length pointed by each address is consistent with the maintenance of the organizational structure of RAM, such as, for the DRAM being organizational structure with byte, in sequence of addresses, the data length pointed by each address is 8, so, first data also are able to the data length pointed with each order and keep consistent with the data length of the second data.
Preferably, described first sequence of addresses is identical with described 3rd sequence of addresses, and described second sequence of addresses is identical with described 4th sequence of addresses, and further, described first sequence of addresses is address incremental order, and described second sequence of addresses is decreasing addresses order；Or described first sequence of addresses is decreasing addresses order, described second sequence of addresses is address incremental order, i.e. read-write operation is all RAM is carried out address sequentially read and write every time, so it is more convenient for determining the address being next time written and read operation, improves the testing efficiency to RAM.
Hereinafter, by a concrete implementation example, the method for testing of the RAM that the embodiment of the present invention provides is described in detail, as shown in Figure 2:
In S201, according to address incremental order, " 0 " is write in all addresses of RAM.
After having performed S201, all address bits of RAM are low level.
In S202, according to decreasing addresses order, all addresses of RAM are performed respectively: verify " 0 " of this bit address, this bit address backward write " 1 ".
Aforesaid operations is accomplished that, verifies and confirms that all address bits of RAM are low level, and being drawn as high level by low level by each address bit of RAM.
In S203, according to address incremental order, all addresses of RAM are performed respectively: verify " 1 " of this bit address, this bit address backward write " 0 ".
Aforesaid operations is accomplished that, verifies and confirms that all address bits of RAM are high level, and being drawn as low level by high level by each address bit of RAM.
In S204, according to decreasing addresses order, all addresses of RAM are performed respectively: verify " 0 " of this bit address.
Aforesaid operations is accomplished that, verifies and confirms that all address bits of RAM are low level.
By the verification operation mentioned in the embodiment of the present invention, the charge status of bit address each in RAM can be tested, to judge whether RAM can correctly carry out discharge and recharge according to the content of read-write operation, this test content covers the various fault models of RAM, and under the premise having ensured fault coverage, shorten the testing time as much as possible.Can be seen that, the method of testing of the RAM that the embodiment of the present invention provides, is only 6n (n is the figure place of RAM) to the test complexity of RAM, and in prior art, the test complexity of MarchC algorithm is 11n, compared to prior art, effectively shorten the testing time.
Should be understood that in above-described embodiment, the size of the sequence number of each step is not meant to the priority of execution sequence, the execution sequence of each process should be determined with its function and internal logic, and the implementation process of the embodiment of the present invention should not constituted any restriction.
Corresponding to the method for testing of the RAM described in foregoing embodiments, Fig. 3 illustrates the structured flowchart of the test device of the RAM that the embodiment of the present invention provides, and for the ease of illustrating, illustrate only part related to the present embodiment.
With reference to Fig. 3, this device includes:
First test cell 31, writes the first data according to the first sequence of addresses to all addresses of RAM；
Second test cell 32, according to the second sequence of addresses, performs to all addresses of described RAM: verify described first data of this address successively, this address backward write the second data, the XOR result of described first data and described second data is 1；
3rd test cell 33, according to the 3rd sequence of addresses, performs to all addresses of described RAM: verify described second data of this address successively, this address backward write the first data；
4th test cell 34, according to the 4th sequence of addresses, performs to all addresses of described RAM: verify described first data of this address successively.
Alternatively, the data mode of described first data and described second data includes position, byte, word or double word.
Alternatively, described first sequence of addresses is identical with described 3rd sequence of addresses, and described second sequence of addresses is identical with described 4th sequence of addresses.
Alternatively, described first sequence of addresses is address incremental order, and described second sequence of addresses is decreasing addresses order；Or
Described first sequence of addresses is decreasing addresses order, and described second sequence of addresses is address incremental order.
Alternatively, described RAM includes dynamic random access memory DRAM.
Those skilled in the art is it can be understood that arrive, for convenience of description and succinctly, only it is illustrated with the division of above-mentioned each functional unit, module, in practical application, as desired above-mentioned functions distribution can be completed by different functional units, module, it is divided into different functional units or module, to complete all or part of function described above by the internal structure of described device.Each functional unit in embodiment, module can be integrated in a processing unit, can also be that unit is individually physically present, can also two or more unit integrated in a unit, above-mentioned integrated unit both can adopt the form of hardware to realize, it would however also be possible to employ the form of SFU software functional unit realizes.It addition, the concrete title of each functional unit, module is also only to facilitate mutually distinguish, it is not limited to the protection domain of the application.The specific works process of unit, module in said system, it is possible to reference to the corresponding process in preceding method embodiment, do not repeat them here.
Those of ordinary skill in the art are it is to be appreciated that the unit of each example that describes in conjunction with the embodiments described herein and algorithm steps, it is possible to being implemented in combination in of electronic hardware or computer software and electronic hardware.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel specifically can should be used for using different methods to realize described function to each, but this realization is it is not considered that beyond the scope of this invention.
In embodiment provided by the present invention, it should be understood that disclosed apparatus and method, it is possible to realize by another way.Such as, system embodiment described above is merely schematic, such as, the division of described module or unit, being only a kind of logic function to divide, actual can have other dividing mode when realizing, for instance multiple unit or assembly can in conjunction with or be desirably integrated into another system, or some features can ignore, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connect the INDIRECT COUPLING that can be through some interfaces, device or unit or communication connects, it is possible to be electrical, machinery or other form.
The described unit illustrated as separating component can be or may not be physically separate, and the parts shown as unit can be or may not be physical location, namely may be located at a place, or can also be distributed on multiple NE.Some or all of unit therein can be selected according to the actual needs to realize the purpose of the present embodiment scheme.
It addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, it is also possible to be that unit is individually physically present, it is also possible to two or more unit are integrated in a unit.Above-mentioned integrated unit both can adopt the form of hardware to realize, it would however also be possible to employ the form of SFU software functional unit realizes.
If described integrated unit is using the form realization of SFU software functional unit and as independent production marketing or use, it is possible to be stored in a computer read/write memory medium.Based on such understanding, part or all or part of of this technical scheme that prior art is contributed by the technical scheme of the embodiment of the present invention substantially in other words can embody with the form of software product, this computer software product is stored in a storage medium, including some instructions with so that a computer equipment (can be personal computer, server, or the network equipment etc.) or processor (processor) perform all or part of step of method described in each embodiment of the embodiment of the present invention.And aforesaid storage medium includes: USB flash disk, portable hard drive, read only memory (ROM, Read-OnlyMemory), the various media that can store program code such as random access memory (RAM, RandomAccessMemory), magnetic disc or CD.
Embodiment described above only in order to technical scheme to be described, is not intended to limit；Although the present invention being described in detail with reference to previous embodiment, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein portion of techniques feature is carried out equivalent replacement；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of each embodiment technical scheme of the embodiment of the present invention.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all any amendment, equivalent replacement and improvement etc. made within the spirit and principles in the present invention, should be included within protection scope of the present invention.
Claims (10)
1. the method for testing of a random access memory ram, it is characterised in that including:
The first data are write to all addresses of RAM according to the first sequence of addresses；
According to the second sequence of addresses, perform successively to all addresses of described RAM: verify described first data of this address, this address backward write the second data, the XOR result of described first data and described second data is 1；
According to the 3rd sequence of addresses, perform successively to all addresses of described RAM: verify described second data of this address, this address backward write the first data；
According to the 4th sequence of addresses, perform successively to all addresses of described RAM: verify described first data of this address.
2. the method for claim 1, it is characterised in that the data mode of described first data and described second data includes position, byte, word or double word.
3. method as claimed in claim 1 or 2, it is characterised in that described first sequence of addresses is identical with described 3rd sequence of addresses, and described second sequence of addresses is identical with described 4th sequence of addresses.
4. method as claimed in claim 3, it is characterised in that described first sequence of addresses is address incremental order, described second sequence of addresses is decreasing addresses order；Or
Described first sequence of addresses is decreasing addresses order, and described second sequence of addresses is address incremental order.
5. method as claimed in claim 1 or 2, it is characterised in that described RAM includes dynamic random access memory DRAM.
6. the test device of a random access memory ram, it is characterised in that including:
First test cell, for writing the first data according to the first sequence of addresses to all addresses of RAM；
Second test cell, for according to the second sequence of addresses, performs to all addresses of described RAM: verify described first data of this address successively, this address backward write the second data, the XOR result of described first data and described second data is 1；
3rd test cell, for according to the 3rd sequence of addresses, performs to all addresses of described RAM: verify described second data of this address successively, this address backward write the first data；
4th test cell, for according to the 4th sequence of addresses, performing successively to all addresses of described RAM: verify described first data of this address.
7. device as claimed in claim 6, it is characterised in that the data mode of described first data and described second data includes position, byte, word or double word.
8. device as claimed in claims 6 or 7, it is characterised in that described first sequence of addresses is identical with described 3rd sequence of addresses, described second sequence of addresses is identical with described 4th sequence of addresses.
9. device as claimed in claim 8, it is characterised in that described first sequence of addresses is address incremental order, described second sequence of addresses is decreasing addresses order；Or
Described first sequence of addresses is decreasing addresses order, and described second sequence of addresses is address incremental order.
10. device as claimed in claims 6 or 7, it is characterised in that described RAM includes dynamic random access memory DRAM.
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| CN107845406A (en) * | 2016-09-20 | 2018-03-27 | 电信科学技术研究院 | A kind of method and apparatus for testing memory |
| CN112420114A (en) * | 2020-11-04 | 2021-02-26 | 深圳市宏旺微电子有限公司 | Fault detection method and device for memory chip |
| CN116259351A (en) * | 2023-05-12 | 2023-06-13 | 粤芯半导体技术股份有限公司 | Memory testing method |
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| CN107845406A (en) * | 2016-09-20 | 2018-03-27 | 电信科学技术研究院 | A kind of method and apparatus for testing memory |
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| CN116259351A (en) * | 2023-05-12 | 2023-06-13 | 粤芯半导体技术股份有限公司 | Memory testing method |
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Application publication date: 20160713 |