CN101197194A - Memory device detecting method - Google Patents
Memory device detecting method Download PDFInfo
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- CN101197194A CN101197194A CNA2007100734274A CN200710073427A CN101197194A CN 101197194 A CN101197194 A CN 101197194A CN A2007100734274 A CNA2007100734274 A CN A2007100734274A CN 200710073427 A CN200710073427 A CN 200710073427A CN 101197194 A CN101197194 A CN 101197194A
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Abstract
The invention discloses a test method for a storage, which mainly includes three test stages which are respectively read-write test, data wire test and address wire test and search for errors existed in the storage through step-by-step exclusive method which makes test results more accurately. Besides, the invention only needs utilizing the initial address and the final address to comprehensively detect whether the data wire has problems; and for detecting the address wire, the comprehensive test can be performed only by utilizing very few address locations. Moreover, through special arrangement of test data, test data groups and test address blocks, specific data wire and address wire on which an error is existed can be pointed out and the error can be reported in time, thereby greatly improving detection efficiency.
Description
Technical field
The present invention relates to the technical field of detection of stored device peripheral circuit and storer quality, especially relate to a kind of to the storer line short with open circuit and the detection method of unit.
Background technology
Storer has been widely used in the various products of computing machine, electronics, the communications industry, and, storer is had relatively high expectations to production technology (for example attachment process), under the not high situation of existing production technology, simultaneously, exist human factor (for example to weld mistake again, cause problems such as rosin joint, adhesion) situation, the problem that storer usually produces short circuit or opens circuit, thus product is made a big impact, product can not normally be moved.Yet, this class problem be difficult to judge by technician's naked eyes usually and therefore the software issue that causes of class hardware problem be difficult for the location and problem is reappeared difficulty.
Proposed a kind of FLASH to be opened circuit and the technical scheme of short-circuit detecting in disclosed Chinese patent CN200410069098.2 on January 26th, 2006 " a kind of detection method of flash memories ", this scheme judges by each address location of FLASH being carried out read-write operation whether its address location has problems, because the time that the FLASH write operation will spend is longer, like this all address locations are all carried out write operation, increased detection time greatly; In addition, in this scheme data line is opened circuit and the testing process of short circuit is very loaded down with trivial details and testing result is also inaccurate, because result who reads and the result who writes are inconsistent, might not be the problems of data line, also might be the problems of address wire or storage unit.Equally, this scheme opens a way and the testing process of short circuit is also very complicated and testing result is inaccurate to address wire.
Summary of the invention
Technical matters to be solved by this invention provides a kind of memory device detecting method, the fault that its which data lines, address wire, storage unit that can detect storer more accurate, more quickly exists, and notify at once.
For solving technical matters of the present invention, the present invention discloses a kind of memory device detecting method, comprising:
Phase one, storer carried out reading and writing detect:
1.1 establishing the first address in a certain sector address space that will detect in the storer is HDDR, the address, end is EDDR, and test data 1 is TD1, and test data 2 is TD2, both bit width equal the data line width that will detect, and TD2 is the step-by-step negate data of TD1;
1.2 write TD1 to HDDR, retaking of a year or grade relatively if the retaking of a year or grade result is unequal, then can be judged storer and have the read-write problem again, stops to detect and Reporting a Problem;
1.3 write TD2 to EDDR, retaking of a year or grade relatively if the retaking of a year or grade result is unequal, then can be judged storer and have the read-write problem again, stops to detect and Reporting a Problem;
1.4 after HDDR and EDDR have write TD1 and TD2 respectively, and all relatively,, then enter subordinate phase and detect if do not pinpoint the problems through retaking of a year or grade;
Subordinate phase, the data line of storer is detected:
Be TDG1 2.1 test data set 1 is set, the data number that it comprised equals the data line width that will detect, and each data is different, and each data is compared with the TD1 that writes HDDR in the step 1.2 and had only a bit different;
2.2 each data of TDG1 are write to HDDR successively, write data at every turn after, retaking of a year or grade relatively if the retaking of a year or grade result equates, then continues to write next data again; If the retaking of a year or grade result is unequal, enter step 2.3;
2.3 according to the retaking of a year or grade result, judge these data that write HDDR and compare that different data lines of bit with TD1 and have fault, and write down this fault, continue to write next data, all detect until all data lines and to finish, stop to detect and reporting the mistake of being found again;
Be TDG2 2.4 test data set 2 is set, the data number that it comprised equals the data line width that will detect, and each data is different, and each data all is the step-by-step negate of corresponding data among the TDG1;
2.5 write TDG2 successively to EDDR, write data at every turn after, retaking of a year or grade relatively if the retaking of a year or grade result equates, then continues to write next data again; If the retaking of a year or grade result is unequal, enter step 2.6;
2.6 according to the retaking of a year or grade result, judge these data that write EDDR and compare that different data lines of bit with TD2 and have fault, and write down this fault, continue to write next data, all detect until all data lines and to finish, stop to detect and reporting the mistake of being found again;
2.7 in 2.1 to 2.6 steps, if do not find the data line existing problems, and the data in TDG1 and the TDG2 all write and retaking of a year or grade finishes, and then enter the phase III detection;
Phase III, memory address line is detected:
3.1 TD1 is write HDDR;
3.2 test address group 1 is set, and it comprises a plurality of test addresses, and each test address compares with HDDR and have only a bit different, and different between each test address;
3.3 the contained data of TDG1 are in turn write in the contained test address of test address group 1, whenever, data have been write to a test address, data in the retaking of a year or grade HDDR again, if the retaking of a year or grade result is TD1, then continue to write next data, all write until all test addresses and finish to next test address; If the retaking of a year or grade result is not TD1, then carry out step 3.4;
3.4 according to the retaking of a year or grade result, judging this test address compares that different root address wire of bit and has fault with HDDR, and write down this fault, continuation writes next data to unit, next test address, all write until all unit, test address and to finish, stop to detect and reporting the mistake of being found;
3.5 TD2 is write EDDR;
3.6 test address group 2 is set, and it comprises a plurality of test addresses, and each test address is the step-by-step negate of test address group 1 contained test address;
3.7 the contained data of TDG2 are write in the contained test address of test address group 2 successively, write once at every turn, the data in the retaking of a year or grade EDDR if the retaking of a year or grade result is TD2, then continue to write next data to next test address again; If the retaking of a year or grade result is not TD2, then carry out step 3.8;
3.8 according to the retaking of a year or grade result, judge this test address and compare that different root address wire of bit with EDDR and have fault, and write down this fault, continue to write next data to next test address, all write until all test addresses and to finish, stop to detect and reporting the mistake of being found.
Compared with prior art, the present invention has following beneficial effect: the present invention is by three detection-phases, classification, progressively analyzes step by step, progressively gets rid of, and makes testing result more accurate; Whether and detection method of the present invention only need be utilized first address and last address, have problems but go out data line with regard to complete detection, to the detection of address wire, equally also only need utilize considerably less address location, just can carry out complete detection; In addition,, can point out it specifically is which data lines and address wire exist fault exactly by special setting to test data, test data set and test address group, and reporting errors in time, thereby detection efficiency improved greatly.
Description of drawings
Fig. 1 is the main flow chart of memory device detecting method of the present invention;
Fig. 2 is the process flow diagram that detects the storer phase one of the present invention;
Fig. 3 is the process flow diagram that storer subordinate phase of the present invention detects;
Fig. 4 is the process flow diagram that detects the storer phase III of the present invention;
Fig. 5 is the process flow diagram that the storer subordinate phase of another embodiment of the present invention detects;
Fig. 6 is the process flow diagram that detects the storer phase III of another embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
As shown in Figure 1, memory device detecting method of the present invention mainly is divided into three detection-phases: the phase one is storer to be done basic reading and writing detect; Subordinate phase is that the data line to storer detects; Phase III is that the address wire to storer detects.
In the present invention, storer is meant that all are followed and exists address wire and data line to connect the readable and writable memory of feature between the CPU, comprises FLASH, RAM, SDRAM etc.
The detection of storer always since the phase one, in the testing process of this three phases, if the wherein a certain stage is detected is out of order, then no longer enters follow-up detection, directly report this fault and stop to detect; If do not detect fault, then carry out follow-up detection again.The condition that promptly starts the latter half detection is not pinpoint the problems in the testing process of previous stage, only in this way could guarantee that it is accurately that the latter half is detected the fault conclusion that is drawn.
As shown in Figure 2, the detection step of phase one comprises:
1.1 establishing the first address in a certain sector address space that will detect in the storer is HDDR, the address, end is EDDR, and test data 1 is TD1, and test data 2 is TD2, both bit width equal the data line width that will detect, and TD2 is the step-by-step negate data of TD1;
1.2 write TD1 to HDDR, retaking of a year or grade relatively if the retaking of a year or grade result is unequal, then can be judged storer and have the read-write problem again, stops to detect and Reporting a Problem;
1.3 write TD2 to EDDR, retaking of a year or grade relatively if the retaking of a year or grade result is unequal, then can be judged storer and have the read-write problem again, stops to detect and Reporting a Problem;
1.4 after HDDR and EDDR have write TD1 and TD2 respectively,, then enter subordinate phase and detect if do not pinpoint the problems.
The address space that HDDR and EDDR can detect according to actual needs is provided with, such as, when a storer with 32M capacity, 8 bit data live widths is detected, if only need detect wherein this sector address space of 0 to 16M, then HDDR is 0X000000, and EDDR is 0XFFFFFF; When a storer with 32M capacity, 16 bit data live widths was detected, if only need detect wherein this sector address space of 0 to 16M, then HDDR was 0X000000, and EDDR is 0XFFFFFE; When a storer with 32M capacity, 32 bit data live widths was detected, if only need detect wherein this sector address space of 0 to 16M, then HDDR was 0X000000, and EDDR is 0XFFFFFC.
TD1 and TD2 step-by-step negate each other data can be convenient to detect storer and whether have the read-write problem.After HDDR writes TD1, the retaking of a year or grade comparative result is not right, illustrate that then there are the read-write problem in HDDR storage unit or data line or address wire,, then further detect again if the retaking of a year or grade comparative result is correct, write TD2 to EDDR, the retaking of a year or grade comparative result is not right, illustrates that then there are the read-write problem in EDDR storage unit or data line or address wire, if the retaking of a year or grade comparative result is correct, then there is not the read-write problem in explanation, and the data line that can enter subordinate phase detects.
In addition,,, after the retaking of a year or grade relatively, write TD1 to HDDR again, also do not influence enforcement of the present invention if write TD2 to EDDR earlier in the phase one.
As shown in Figure 3, the detection step of subordinate phase comprises:
Be TDG1 2.1 test data set 1 is set, the data number that it comprised equals the data line width that will detect, and each data is different, and each data is compared with the TD1 that writes HDDR in the step 1.2 and had only a bit different;
2.2 each data of TDG1 are write to HDDR successively, write data at every turn after, retaking of a year or grade relatively if the retaking of a year or grade result equates, then continues to write next data again; If the retaking of a year or grade result is unequal, enter step 2.3;
2.3 according to the retaking of a year or grade result, judge these data that write HDDR and compare that different data lines of bit with TD1 and have fault, and write down this fault, continue to write next data, all detect until all data lines and to finish, stop to detect and reporting the mistake of being found again;
Be TDG2 2.4 test data set 2 is set, the data number that it comprised equals the data line width that will detect, and each data is different, and each data all is the step-by-step negate of corresponding data among the TDG1;
2.5 write TDG2 successively to EDDR, write data at every turn after, retaking of a year or grade relatively if the retaking of a year or grade result equates, then continues to write next data again; If the retaking of a year or grade result is unequal, enter step 2.6;
2.6 according to the retaking of a year or grade result, judge these data that write EDDR and compare that different data lines of bit with TD2 and have fault, and write down this fault, continue to write next data, all detect until all data lines and to finish, stop to detect and reporting the mistake of being found again;
2.7 in 2.1 to 2.6 steps,, have data in TDG1 and the TDG2 all to write and retaking of a year or grade finishes, then enter the phase III to detect if find data line existing problems;
Be all data lines of complete detection, the number of test data set TDG1 and TDG2 equals the data line width, there is fault for accurately detecting any data lines, the data of TDG1 all are set to compare with TD1 have only a bit different, the special data that other are identical, TDG2 is made as the negate of TDG1, is to go out the short circuit of data line and the problem that opens circuit for complete detection.
Such as, the testing data line width is 8, and TD1 is set to " 00000000B ", and TD2 is " 11111111B "; Then TDG1 is the combination of " 00000001B ", " 00000010B ", " 00000100B ", " 00001000B ", " 00010000B ", " 00100000B ", " 01000000B ", " 10000000B "; TDG2 is the " combination of " 111110B ", " 11111101B ", " 11111011B ", " 11110111B ", " 11101111B ", " 11011111B ", " 10111111B ", " 01111111B ".
In addition, step 2.1 is exchanged with step 2.4 to 2.6 sequencings to 2.3, does not also influence enforcement of the present invention.
As shown in Figure 4, the detection step of phase III comprises:
3.1 TD1 is write HDDR;
3.2 test address group 1 is set, and the sum of its contained test address equals the required address wire figure place of the described address space of step 1.1, and each test address compares with HDDR and have only a bit different, and different between each test address;
3.3 the contained data of TDG1 are in turn write in the contained test address of test address group 1, whenever, data have been write to a test address, data in the retaking of a year or grade HDDR again, if the retaking of a year or grade result is TD1, then continue to write next data, all write until all test addresses and finish to next test address; If the retaking of a year or grade result is not TD1, then carry out step 3.4;
3.4 according to the retaking of a year or grade result, judging this test address compares that different root address wire of bit and has fault with HDDR, and write down this fault, continuation writes next data to unit, next test address, all write until all unit, test address and to finish, stop to detect and reporting the mistake of being found;
3.5 TD2 is write EDDR;
3.6 test address group 2 is set, and it comprises a plurality of test addresses, and each test address is the step-by-step negate of test address group 1 contained test address;
3.7 the contained data of TDG2 are write in the contained test address of test address group 2 successively, write once at every turn, the data in the retaking of a year or grade EDDR if the retaking of a year or grade result is TD2, then continue to write next data to next test address again; If the retaking of a year or grade result is not TD2, then carry out step 3.8;
3.8 according to the retaking of a year or grade result, judge this test address and compare that different root address wire of bit with EDDR and have fault, and write down this fault, continue to write next data to next test address, all write until all test addresses and to finish, stop to detect and reporting the mistake of being found.
In the phase III, for intactly detecting all address wires, test address group 1 is set preferably and group 2 contained test address numbers in test address equal the address wire width, but situation about can not read and write according to the odd address of actual storage sometimes, the test address number can be less than the address wire width.There is fault for detecting any root address wire more accurately, then has only a bit different for comparing all address setting in the test address group 1, the address location that other are identical with HDDR.Test address group 2 is made as the step-by-step negate of test address group 1, is to go out the short circuit of address wire and the problem that opens circuit for complete detection.
Such as HDDR is " 00000B ", then test address group 1 is the combination of " 00001B ", " 00010B ", " 00100B ", " 01000B ", " 10000B ", and test address group 2 is the combination of " 11110B ", " 11101B ", " 11011B ", " 10111B ", " 01111B ".
Owing to there be the situation of the address wire width of storer greater than the data line width, so all data in TDG1 have all write test address group 1, do not write data and test address group 1 also has address space left,, step 3.3 be may further comprise the steps for detecting remaining address:
3.3.1 the data in the TDG1 are write once more the address space left of test address group 1 since M (M is the integer less than the contained data total data of TDG1);
All data in described TDG2 have all write test address group 2, and test address group 2 is when also having address space left not write data, and described step 3.7 also comprises step:
3.7.1 the data in the TDG2 are write once more the address space left of test address group 2 since N (N is the integer less than the contained data total data of TDG1).
Step 3.1 is exchanged with step 3.5 to 3.8 sequencings to 3.4, does not also influence enforcement of the present invention.
Below detect 16 position datawire (D with need
15D
14D
13... D
0), 25 bit address line (A
24A
23A
22... A
0) storer be example, the present invention is described in detail in detail.
Embodiment 1
Phase one, read-write detect:
1, HDDR is 0X0000000, owing to the odd address of storer can not be read and write, so EDDR is 0X1FFFFFE; For ease of detecting and computing, TD1 is made as " complete 0 ", i.e. 0X0000, TD2 is made as " complete 1 ", i.e. 0XFFFF,
TD1 and TD2 can exchange, and enforcement of the present invention is not influenced, and the reason that TD1 and TD2 are set to " complete 0 " and " complete 1 " is the setting of being convenient to TDG1 and the TDG2 of follow-up subordinate phase and phase III;
2, TD1 is write HDDR, retaking of a year or grade relatively, if the result is correct, meaning then that every data lines is put low level ' 0 ' can be normal, can get rid of data line and exist and permanently be the problem of high level ' 1 ', then, enters next step; If the result is incorrect, HDDR or address wire or data line reading and writing existing problems then are described, stop to detect and Reporting a Problem;
3, TD2 is write EDDR, retaking of a year or grade relatively, if the result is correct, meaning then that every data lines is put high level " 1 " can be normal, can get rid of data line and exist and permanently be the problem of low level ' 0 ' then, to enter the detection of subordinate phase; If the result is incorrect, EDDR or address wire or data line reading and writing existing problems then are described, stop to detect and Reporting a Problem.
Subordinate phase, data line detect:
1, establishing the contained data of TDG1 comprises: 0X0001,0X0002,0X0004,0X0008,0X0010,0X0020,0X0040,0X0080,0X0100,0X0200,0X0400,0X0800,0X1000,0X2000,0X4000,0X8000;
2,16 data with TDG1 write in the HDDR successively, whenever write once, and retaking of a year or grade once if the retaking of a year or grade result is correct, then continues to write, and all writes retaking of a year or grade up to 16 data and finishes, and does not also pinpoint the problems, and then enters step 4;
3, if the retaking of a year or grade result is incorrect, then according to the data of retaking of a year or grade, can judge in the data that write HDDR is the bit corresponding data lines existing problems of " 1 ", write down this problem, continue to write remainder data again, finish, stop to detect and reporting the problem of being found up to writing retaking of a year or grade;
Such as, after all data in the above-mentioned TDG1 are write HDDR and finish, find that there are following two faults in storer, then report this two faults, and stop to detect:
(1) writing data is 0X0001, and sense data is 0X0000, then can judge data line D
0There is open circuit fault;
(2) writing data is 0X0010, and sense data is 0X0000, then can judge data line D
4There is open circuit fault;
4, establishing the contained data of TDG2 comprises: 0XFFFE, 0XFFFD, 0XFFFB, 0XFFF7,0XFFEF, 0XFFDF, 0XFFBF, 0XFF7F, 0XFEFF, 0XFDFF, 0XFBFF, 0XF7FF, 0XEFFF, 0XDFFF, 0XBFFF, 0X7FFF;
5,16 of TDG2 data write in the EDDR successively, whenever write once, and retaking of a year or grade once if the retaking of a year or grade result is correct, then continues to write, and all write and retaking of a year or grade finishes up to 16 data, also do not pinpoint the problems, and then enter the detection of phase III;
6, if the retaking of a year or grade result is incorrect, then according to the data of retaking of a year or grade, can judge in the data that write EDDR is the bit corresponding data lines existing problems of " 0 ", write down this problem, continue to write remainder data again, finish, stop to detect and reporting the problem of being found up to writing;
Such as, after all data in the above-mentioned TDG2 are write EDDR and finish, find that there are following two faults in storer, then report this two faults, and stop to detect:
(1) writing data is 0XFFFE, and sense data is 0XFFFF, then can judge data line D
0There is short trouble;
(2) writing data is 0XFFEF, and sense data is 0XFFFF, then can judge data line D
4There is short trouble;
7, if TDG1 and TDG2 writes HDDR respectively and EDDR finishes, and do not pinpoint the problems, then enter the phase III to detect.
Phase III, address wire detect:
1, TD1 is write HDDR, be about to data 0X0000 and write 0X0000000;
2, owing to be 16 bit data bit wides, the test address is necessary for even address, so the combination of test address group 1 for 0X0000002,0X0000004,0X0000008,0X0000010,0X0000020,0X0000040,0X0000080,0X0000100,0X0000200,0X0000400,0X0000800,0X0001000,0X0002000,0X0004000,0X0008000,0X0010000,0X0020000,0X0040000,0X0080000,0X0100000,0X0200000,0X0400000, these 24 address locations of 0X0800000,0X1000000 is set;
TDG1 is write above-mentioned test address group 1 successively, and after 16 data had write test address group 1 in the TDG1, test address group 1 also had remaining address not test, and then continued to begin to write successively from first data of TDG1, and is as follows:
TDG1: test address group 1:
0X0001------------------------0X0000002
0X0002------------------------0X0000004
0X0004------------------------0X0000008
……
0X0020------------------------0X0400000
0X0040------------------------0X0800000
0X0080------------------------0X1000000
Data after at every turn having write in the retaking of a year or grade 0X0000000 if the retaking of a year or grade result is 0X0000, then continue to write next data to next address, and all addresses in test address group 1 all write to read and finish, and do not pinpoint the problems, and then enter step 4;
3, if the retaking of a year or grade result is not 0X0000, illustrate that then comparing that different root address wire of bit with HDDR exists fault, write down this fault, continue to write again, all addresses in test address group 1 all write to read and finish, and stop to detect and reporting errors;
Such as:
(1) 0X0002 is write 0X0000002 after, the data in the retaking of a year or grade 0X0000000, the retaking of a year or grade result is 0X0002, and address wire A is described
1There is the problem that opens circuit, the content that writes the 0X0000002 address has originally been write the 0X0000000 address;
(2) 0X0010 is write 0X0000010 after, the data in the retaking of a year or grade 0X0000000, the retaking of a year or grade result is 0X0010, and address wire A is described
4There is the problem that opens circuit, the content that writes the 0X0000010 address has originally been write the 0X0000000 address;
4, TD2 is write EDDR, be about to 0XFFFF and write in the 0X1FFFFFE;
5, test address group 2 is set is 0X1FFFFFC, 0X1FFFFFA, 0X1FFFFF6,0X1FFFFEE, 0X1FFFFDE, 0X1FFFFBE, 0X1FFFF7E, 0X1FFFEFE, 0X1FFFDFE, 0X1FFFBFE, 0X1FFF7FE, 0X1FFEFFE, 0X1FFDFFE, 0X1FFBFFE, 0X1FF7FFE, 0X1FEFFFE, 0X1FDFFFE, 0X1FBFFFE, 0X1F7FFFE, 00X1EFFFFE, 0X1DFFFFE, 0X1BFFFFE, 0X17FFFFE, the combination of these 24 address locations of 0X0FFFFFE;
TDG2 is write above-mentioned test address group 2 successively, and after 16 data had write test address group 2 in the TDG1, test address group 2 also had remaining address not test, and then continued to begin to write successively from first data of TDG1, and is as follows:
TDG2: test address group 2:
0XFFFE------------------------0X1FFFFFC
0XFFFD------------------------0X1FFFFFA
0XFFFB------------------------0X1FFFFF6
0XFFF7------------------------0X1FFFFEE
0XFFEE------------------------0X1DFFFEE
0XFFDE------------------------0X1BFFFEE
0XFFBE------------------------0X17FFFEE
0XFF7E------------------------0X0FFFFEE
Data after at every turn having write in the retaking of a year or grade 0X1FFFFFE, if the retaking of a year or grade result is 0XFFFF, then continue to write next data to next address, all addresses in test address group 2 all write to read and finish, if do not pinpoint the problems, read-write, data line and the address wire that then can judge this storer do not have fault;
6, if the retaking of a year or grade result is not 0XFFFF, illustrate that then comparing that different root address wire of bit with EDDR exists fault, write down this fault, continue to write again, all addresses in test address group 2 all write and finish, and stop to detect and reporting errors;
Such as:
(1) 0XFFFE is write 0X1FFFFFC after, the data in the retaking of a year or grade 0X1FFFFFE, the retaking of a year or grade result is 0XFFFE, and address wire A is described
1There is short circuit problem, the content that writes the 0X1FFFFFC address has originally been write the 0X1FFFFFE address;
(2) 0XFFF7 is write 0X1FFFFEE after, the data in the retaking of a year or grade 0X1FFFFFE, the retaking of a year or grade result is 0XFFF7, and address wire A is described
4There is short circuit problem, the content that writes the 0X1FFFFEE address has originally been write the 0X1FFFFFE address;
By the detection of above-mentioned three phases, can detect read-write problem, data line and the address wire problem of storer accurately, all sidedly, and it is simple, convenient to detect step, does not need to carry out a large amount of read-write operations, and detection speed is improved greatly.
Because dissimilar storeies and different periphery circuit design, same result can represent different problems, and such as in subordinate phase the 3rd goes on foot, same retaking of a year or grade result for the storer of some type, may be D
0And D
4There is short trouble, so in actual applications, needs the professional to make correct problem and judge according to the particular hardware schematic diagram.
Embodiment 2
The difference of present embodiment and embodiment 1 is: in the subordinate phase of embodiment 1 with in the phase III, there is fault if find certain data lines or address wire, then write down this fault, continue again to detect, and in the present embodiment, in subordinate phase and phase III, as long as one finds that there are fault in data line or address wire, then stop to detect, report this problem, after treating that this fault is got rid of, again storer is restarted to detect.The testing process of present embodiment subordinate phase and phase III, respectively as shown in Figure 5 and Figure 6.
Claims (10)
1. a memory device detecting method is characterized in that, comprising:
Phase one, storer carried out reading and writing detect:
1.1 establishing the first address in a certain sector address space that will detect in the storer is HDDR, last address is EDDR, and test data 1 is TD1, and test data 2 is TD2, and both bit width equal the data line width that will detect; And TD2 is the step-by-step negate data of TD1;
1.2 write TD1 to HDDR, retaking of a year or grade relatively if the retaking of a year or grade result is unequal, then can be judged storer and have the read-write problem again, stops to detect and Reporting a Problem;
1.3 write TD2 to EDDR, retaking of a year or grade relatively if the retaking of a year or grade result is unequal, then can be judged storer and have the read-write problem again, stops to detect and Reporting a Problem;
1.4 after HDDR and EDDR have write TD1 and TD2 respectively, and all relatively,, then enter subordinate phase and detect if do not pinpoint the problems through retaking of a year or grade;
Subordinate phase, the data line of storer is detected:
Be TDG1 2.1 test data set 1 is set, the data number that it comprised equals the data line width that will detect, and each data is different, and each data is compared with the TD1 that writes HDDR in the step 1.2 and had only a bit different;
2.2 each data of TDG1 are write to HDDR successively, write data at every turn after, retaking of a year or grade relatively if the retaking of a year or grade result equates, then continues to write next data again; If the retaking of a year or grade result is unequal, enter step 2.3;
2.3 according to the retaking of a year or grade result, judge these data that write HDDR and compare that different data lines of bit with TD1 and have fault, and write down this fault, continue to write next data, all detect until all data lines and to finish, stop to detect and reporting the mistake of being found again;
Be TDG2 2.4 test data set 2 is set, the data number that it comprised equals the data line width that will detect, and each data is different, and each data all is the step-by-step negate of corresponding data among the TDG1;
2.5 write TDG2 successively to EDDR, write data at every turn after, retaking of a year or grade relatively if the retaking of a year or grade result equates, then continues to write next data again; If the retaking of a year or grade result is unequal, enter step 2.6;
2.6 according to the retaking of a year or grade result, judge these data that write EDDR and compare that different data lines of bit with TD2 and have fault, and write down this fault, continue to write next data, all detect until all data lines and to finish, stop to detect and reporting the mistake of being found again;
2.7 in 2.1 to 2.6 steps, if do not find the data line existing problems, and the data in TDG1 and the TDG2 all write and retaking of a year or grade finishes, and then enter the phase III detection;
Phase III, memory address line is detected:
3.1 TD1 is write HDDR;
3.2 test address group 1 is set, and it comprises a plurality of test addresses, and each test address compares with HDDR and have only a bit different, and different between each test address;
3.3 the contained data of TDG1 are in turn write in the contained test address of test address group 1, whenever, data have been write to a test address, data in the retaking of a year or grade HDDR again, if the retaking of a year or grade result is TD1, then continue to write next data, all write until all test addresses and finish to next test address; If the retaking of a year or grade result is not TD1, then carry out step 3.4;
3.4 according to the retaking of a year or grade result, judging this test address compares that different root address wire of bit and has fault with HDDR, and write down this fault, continuation writes next data to unit, next test address, all write until all unit, test address and to finish, stop to detect and reporting the mistake of being found;
3.5 TD2 is write EDDR;
3.6 test address group 2 is set, and it comprises a plurality of test addresses, and each test address is the step-by-step negate of test address group 1 contained test address;
3.7 the contained data of TDG2 are write in the contained test address of test address group 2 successively, write once at every turn, the data in the retaking of a year or grade EDDR if the retaking of a year or grade result is TD2, then continue to write next data to next test address again; If the retaking of a year or grade result is not TD2, then carry out step 3.8;
3.8 according to the retaking of a year or grade result, judge this test address and compare that different root address wire of bit with EDDR and have fault, and write down this fault, continue to write next data to next test address, all write until all test addresses and to finish, stop to detect and reporting the mistake of being found.
2. memory device detecting method according to claim 1 is characterized in that, described TD1 and TD2 are respectively " complete 0 " and " complete 1 " both select one.
3. memory device detecting method according to claim 1 is characterized in that, all data in described TDG1 have all write test address group 1, and test address group 1 is when also having address space left not write data, and described step 3.3 also comprises step:
3.3.1 the data in the TDG1 are write once more the address space left of test address group 1 since M;
All data in described TDG2 have all write test address group 2, and test address group 2 is when also having address space left not write data, and described step 3.7 also comprises step:
3.7.1 the data in the TDG2 are write once more the address space left of test address group 2 since N.
4. memory device detecting method according to claim 1 is characterized in that, directly stops to detect and reporting errors after concrete which the in-problem step of data lines of the judgement of described step 2.3.
5. according to claim 1 or 4 described memory device detecting methods, it is characterized in that after concrete any the data lines in-problem step of the judgement of described step 2.6, directly stop to detect and reporting errors.
6. memory device detecting method according to claim 1 is characterized in that, directly stops to detect and reporting errors after the concrete in-problem step of which root address wire of the judgement of described step 3.4.
7. according to claim 1 or 6 described memory device detecting methods, it is characterized in that, after the concrete in-problem step of any root address wire of the judgement of described step 3.8, directly stop to detect and reporting errors.
8. memory device detecting method according to claim 1 is characterized in that, described step 1.2 and step 1.3 sequencing exchange.
9. according to claim 1 or 4 described memory device detecting methods, it is characterized in that described step 2.1 is exchanged with step 2.4 to 2.6 sequencings to 2.3.
10. according to claim 1 or 4 or 5 described memory device detecting methods, it is characterized in that described step 3.1 is exchanged with step 3.5 to 3.8 sequencings to 3.4.
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