CN112000536A - Memory detection method, system and related equipment - Google Patents
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Abstract
The embodiment of the invention provides a memory detection method, a memory detection system and related equipment, which are used for identifying specific fault types in a DDR memory and improving the accuracy of memory detection. The method provided by the embodiment of the invention comprises the following steps: sequentially writing data into a DDR memory when one effective position in the data line is low and the other effective positions are high, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data; sequentially enabling one effective position in the data lines to be high and the other effective positions to be low, writing data into the DDR memory, and judging whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data; when the data line is judged to have no short circuit or open circuit fault, writing preset data into storage units corresponding to all available addresses of the DDR memory, and then judging whether the DDR memory has a hardware fault according to the consistency of the read back data and the preset data.
Description
Technical Field
The present invention relates to the field of memory detection technologies, and in particular, to a memory detection method, system and related device.
Background
In an embedded device, the stability of a DDR RAM (Double Data Rate Access Memory, referred to as a DDR Memory for short) is crucial to the reliability of the whole system, and therefore, it is necessary to detect the DDR Memory commonly used in hardware.
When a traditional embedded device carries out DDR memory test, preset data are written into storage spaces corresponding to all available addresses of a DDR memory, then the data are read back, the consistency of the data is detected, and if the read back data and the written data are different, the DDR memory is judged to have faults.
In the existing scheme, whether the DDR memory has a fault can be detected, but the fault cannot be located. In view of the above, a new memory detection method is needed.
Disclosure of Invention
The embodiment of the invention provides a memory detection method, a memory detection system and related equipment, which are used for identifying specific fault types in a DDR memory and improving the accuracy of memory detection.
A first aspect of an embodiment of the present invention provides a memory detection method, which may include:
sequentially writing data into a DDR memory when one effective position in the data line is low and the other effective positions are high, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data;
sequentially enabling one effective position in the data lines to be high and the other effective positions to be low, writing data into the DDR memory, and judging whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
when the data line is judged to have no short circuit or open circuit fault, writing preset data into storage units corresponding to all available addresses of the DDR memory, and then judging whether the DDR memory has a hardware fault according to the consistency of the read back data and the preset data.
Optionally, as a possible implementation manner, the memory detection method in the embodiment of the present invention may further include:
sequentially writing data into a DDR memory when one effective position in address lines is low and the other effective positions are high, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
and sequentially writing data into the DDR memory when one effective position in the address lines is high and the other effective positions are low, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data.
Optionally, as a possible implementation manner, in the embodiment of the present invention, writing preset data in a storage unit corresponding to all available addresses of the DDR memory may include:
and writing 0 into the data bits of the storage units corresponding to all available addresses of the DDR memory, and then writing 1 into the data bits of the storage units corresponding to all available addresses of the DDR memory.
Optionally, as a possible implementation manner, in the embodiment of the present invention, writing preset data in a storage unit corresponding to all available addresses of the DDR memory may include:
writing own memory address data into each storage unit of the DDR memory, and then rewriting complement data corresponding to the own memory address into each storage unit of the DDR memory.
A second aspect of the present invention provides a memory detection system, which may include:
the first detection module is used for sequentially writing data into the DDR memory when an effective position in the data line is low and other positions are high, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data;
the second detection module is used for sequentially writing data into the DDR memory when one effective position in the data line is high and the other effective positions are low, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data;
and the third detection module writes preset data into storage units corresponding to all available addresses of the DDR memory when the data line is judged to have no short circuit or open circuit fault, and then judges whether the DDR memory has hardware fault according to the consistency of the read back data and the preset data.
Optionally, as a possible implementation manner, the memory detection system in the embodiment of the present invention may further include:
the fourth detection module is used for sequentially writing data into the DDR memory when one effective position in the address lines is low and the other effective positions are high, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
and the fifth detection module is used for sequentially writing data into the DDR memory when one effective position in the address lines is high and the other effective positions are low, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data.
Optionally, as a possible implementation manner, the third detection module in the embodiment of the present invention may include:
and the first detection unit writes 0 in all the data bits of the storage units corresponding to all the available addresses of the DDR memory, and then writes 1 in all the data bits of the storage units corresponding to all the available addresses of the DDR memory.
Optionally, as a possible implementation manner, the third detection module in the embodiment of the present invention may include:
and the second detection unit writes own memory address data into each storage unit of the DDR memory, and then rewrites complement data corresponding to the own memory address into each storage unit of the DDR memory.
A third aspect of embodiments of the present invention provides a computer apparatus, which includes a processor, and the processor is configured to implement the steps in any one of the possible implementation manners of the first aspect and the first aspect when executing a computer program stored in a memory.
A fourth aspect of the embodiments of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps in any one of the possible implementations of the first aspect and the first aspect.
According to the technical scheme, the embodiment of the invention has the following advantages:
in the embodiment of the invention, the memory detection system can write data into the DDR memory by sequentially lowering one effective position and raising the other effective positions in the data lines, and judge whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data; sequentially enabling one effective position in the data lines to be high and the other effective positions to be low, writing data into the DDR memory, and judging whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data; when the data line is judged to have no short circuit or open circuit fault, writing preset data into storage units corresponding to all available addresses of the DDR memory, and then judging whether the DDR memory has a hardware fault according to the consistency of the read data and the preset data. Compared with the related technology, the embodiment of the invention increases the dimension of DDR memory detection, can identify the specific fault type of the data line in the DDR memory, and improves the accuracy of memory detection.
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Fig. 1 is a schematic diagram of an embodiment of a memory detection method according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another embodiment of a memory detection method according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an embodiment of a memory detection method according to the present invention;
FIG. 4 is a diagram illustrating a data bit level high and low cycle setting in an embodiment of the invention;
FIG. 5 is a diagram illustrating a memory detection system according to an embodiment of the present invention;
FIG. 6 is a diagram of a computer device according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a memory detection method, a memory detection system and related equipment, which are used for identifying specific fault types in a DDR memory and improving the accuracy of memory detection.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the related art, whether the DDR memory has a fault is determined only according to the consistency of the data written in and read out from the memory cell of the DDR memory, and the specific fault type cannot be located. Applicants have noted that a DDR memory failure can be caused by a short or open data line, a hardware problem of a memory cell (a cell can only maintain a high state or a low state, i.e. can only be in a "0" state or a "1" state, when storing a "0", a read may be a "1", or a read of a "1" may be a "0"). Therefore, the embodiment of the invention carries out short circuit/open circuit and fault detection on the corresponding data written in the data line, the address line and the memory unit, and accurately positions the fault.
For convenience of understanding, a detailed process in the embodiment of the present invention is described below, and referring to fig. 1, an embodiment of a memory detection method in the embodiment of the present invention may include:
s101, sequentially enabling one effective position in the data line to be low and the other effective positions to be high, writing data into a DDR memory, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data;
in order to identify whether the data line has a short circuit/open circuit and a fault, the memory detection system in the embodiment of the invention can sequentially write data into the DDR memory with one effective position low and the other effective positions high, and judge whether the data line has the short circuit or open circuit fault according to the consistency of the written data and the read data.
For example, taking a 32-bit data line as an example, the least significant bit may be first written to the DDR RAM for verification, the remaining bits are first written to high (11111111111111111111111111111111111111111110), then the next lower bit (i.e., bit1) is written to low (11111111111111111111111111111101), the remaining bits are written to high, and so on, the test cycle may be completed by moving 1 bit each time until the most significant bit is low and the other bits are high. When the written data bit is at high level (1) and the read data bit is at low level (0), it can be determined that the corresponding data line has an open circuit fault, whereas when the written data bit is at low level (0) and the read data bit is at high level (1), it can be determined that the corresponding data line has a short circuit fault.
S102, sequentially enabling one effective position in the data line to be high and the other effective positions to be low, writing data into a DDR memory, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data;
in order to further identify whether the data line has a short circuit/open circuit and a fault, the memory detection system in the embodiment of the invention can also sequentially write data into the DDR memory with one effective position high and the other effective positions low, and judge whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data. It is understood that the order of steps 101 and 102 may be changed according to actual requirements, and is not limited herein.
For example, taking a 32-bit data line as an example, the data line may be first written into the DDR RAM with the least significant bit high and the rest low (00000000000000000000000000000001) for verification, then the next lower bit (i.e., bit0) is set to high (00000000000000000000000000000010), the rest low, and so on, and the test may be completed by shifting 1 bit each time until the most significant bit is high and the other bits are low. When the written data bit is at high level (1) and the read data bit is at low level (0), it can be determined that the corresponding data line has an open circuit fault, whereas when the written data bit is at low level (0) and the read data bit is at high level (1), it can be determined that the corresponding data line has a short circuit fault.
S103, when the data line is judged to have no short circuit or open circuit fault, writing preset data into storage units corresponding to all available addresses of the DDR memory, and then judging whether the DDR memory has a hardware fault according to the consistency of the read back data and the preset data.
When it is determined that the data line has no short circuit or open circuit fault, the memory detection system in the embodiment of the invention may further write preset data in the memory cells corresponding to all available addresses of the DDR memory, and then determine whether the DDR memory has a hardware fault according to the consistency of the read back data and the preset data.
Optionally, as a possible implementation manner, in the embodiment of the present invention, writing preset data in a memory unit corresponding to all available addresses of a DDR memory may include: and writing 0 into the data bits of the memory cells corresponding to all available addresses of the DDR memory, and then writing 1 into the data bits of the memory cells corresponding to all available addresses of the DDR memory.
Specifically, the memory detection system may traverse the storage units corresponding to all the memory addresses, write the data bits of the traversed storage units into 0, and read the written data to perform fault identification; and then traversing the storage units corresponding to all the memory addresses again, writing the data bits of the traversed storage units into 1, and reading the written data for fault identification.
Optionally, as a possible implementation manner, in the embodiment of the present invention, writing preset data in a memory unit corresponding to all available addresses of a DDR memory may include: writing own memory address data into each storage unit of the DDR memory, and then rewriting complement data corresponding to the own memory address into each storage unit of the DDR memory.
For example, for a memory cell with a memory address of 0 xfffff FFFF, data 0 xfffff FFFF is written first, and the written data is read for fault identification; and then the complement data corresponding to the data 0xFFFF FFFF is rewritten.
In the embodiment of the invention, the memory detection system can write data into the DDR memory by sequentially lowering one effective position and raising the other effective positions in the data lines, and judge whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data; sequentially enabling one effective position in the data lines to be high and the other effective positions to be low, writing data into the DDR memory, and judging whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data; when the data line is judged to have no short circuit or open circuit fault, writing preset data into storage units corresponding to all available addresses of the DDR memory, and then judging whether the DDR memory has a hardware fault according to the consistency of the read data and the preset data. Compared with the related technology, the embodiment of the invention increases the dimension of DDR memory detection, can identify the specific fault type of the data line in the DDR memory, and improves the accuracy of memory detection.
On the basis of the embodiment shown in fig. 1, when it is determined that the data line has no short circuit or open circuit fault and a hardware fault of the DDR memory is identified, the fault may be a fault of the address line and a hardware fault of the memory cell, and further detection is required for this purpose. Referring to fig. 2, an embodiment of a memory detection method according to an embodiment of the present invention may include:
s201, sequentially enabling one effective position of the data lines to be low and the other effective positions to be high, writing data into a DDR memory, and judging whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
s202, sequentially enabling one effective position in the data lines to be high and the other effective positions to be low, writing data into a DDR memory, and judging whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
the content described in steps 201 to 202 in the embodiment of the present invention is similar to the content described in steps 101 to 102 shown in fig. 1, and is not described herein again.
S203, sequentially enabling one effective position in the address lines to be low and the other effective positions to be high, writing data into the DDR memory, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
in order to identify whether the address lines have short circuit/open circuit and faults, the memory detection system in the embodiment of the invention can sequentially write data into the DDR memory with a low effective position and high other positions in the address lines, and judge whether the address lines have short circuit or open circuit faults according to the consistency of the written data and the read data.
For example, taking 32-bit address lines as an example, the least significant bit may be first written to the DDR RAM with the remaining bits high (11111111111111111111111111111111111111111110) for verification, then the next lower bit (i.e., bit1) may be written to the DDR RAM with the remaining bits high (11111111111111111111111111111101), and so on, moving 1 bit each time until the most significant bit is low and the other bits are high, and then completing one round of testing. When the written data bit is at high level (1) and the read data bit is at low level (0), the corresponding address line can be judged to have open circuit fault, whereas when the written data bit is at low level (0) and the read data bit is at high level (1), the corresponding address line can be judged to have short circuit fault.
S204, sequentially enabling one effective position in the address lines to be high and the other effective positions to be low, writing data into the DDR memory, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
in order to further identify whether the address lines have short circuit/open circuit and faults, the memory detection system in the embodiment of the invention can also sequentially write data into the DDR memory by setting one effective position in the address lines to be high and setting the other effective positions to be low, and judge whether the address lines have short circuit or open circuit faults according to the consistency of the written data and the read data.
For example, taking 32-bit address lines as an example, the least significant bit may be first written into the DDR RAM for verification, the remaining bits are then written into the DDR RAM (00000000000000000000000000000001) and then the next lower bit (i.e., bit0) is set to high level (00000000000000000000000000000010), the remaining bits are set to low level, and so on, the test cycle may be completed by moving 1 bit each time until the most significant bit is high level and the other bits are low level. When the written data bit is at high level (1) and the read data bit is at low level (0), the corresponding address line can be judged to have open circuit fault, whereas when the written data bit is at low level (0) and the read data bit is at high level (1), the corresponding address line can be judged to have short circuit fault.
S205, when the data line and the address line are judged to have no short circuit or open circuit fault, writing preset data into the storage units corresponding to all available addresses of the DDR memory, and then judging whether the hardware fault exists in the storage units in the DDR memory according to the consistency of the read back data and the preset data.
When the data line and the address line are judged to have no short circuit or open circuit fault, writing preset data into the storage units corresponding to all available addresses of the DDR memory, and judging whether the hardware fault exists in the storage units in the DDR memory according to the consistency of the read-back data and the preset data. Specifically, the step 103 in the embodiment shown in fig. 1 may be referred to in the process of writing the preset data in the memory cells corresponding to all the available addresses of the DDR memory, which is not described herein again.
Compared with the related technology, the embodiment of the invention increases the dimension of DDR memory detection, can identify the specific fault type of a data line and an address line in the DDR memory, can also locate the hardware fault in a specific storage unit, and improves the accuracy of memory detection.
For convenience of understanding, the memory detection method in the embodiment of the present invention will be described below with reference to a specific application embodiment, and with reference to fig. 3, the method specifically includes the following steps:
data line detection process: the least significant bit is written into the DDR memory for verification, the next lower bit (bit 1) is set to be low, the other positions are set to be high, and the like, 1 bit is moved each time until the most significant bit is low, and the other bits are high, so that one round of test can be completed. And in the second round of test, the lowest effective position is firstly high, the rest positions are low, then the lowest effective position is sequentially high towards the highest effective position bit by bit, the highest effective position is moved by 1 bit each time, and the set detection data is opposite to that of the first round. These two operations are used to detect short and open conditions of the data lines and the data bit level high and low cycling is set as shown in fig. 4.
An address line detection flow: the detection of the address line is also intended to detect short/open circuit, so that the data line detection method can be used for testing. The address line is written into the memory cell for verification after the address line is high level from the least significant bit to the most significant position and low level at the rest positions bit by bit. After the test is finished, the low level is tested from the low level to the high level by the low level.
A storage unit detection process: a hardware problem may exist in the memory cell, which causes a certain cell to only keep high level or low level state, i.e. only to be in "0" state or "1" state. When a "0" is stored, the read-out may be a "1", or a "1" is stored and read-out is a "0". There are two approaches to detect this problem: in the first scheme, 0 is firstly written into each unit, then the unit is inverted, and the unit is tested after being fully written with 1; the second scheme is that the address of the memory unit is written into the memory unit, and the complement of the address is written into the memory unit after reading and comparison.
In this embodiment, the short/open circuit condition of the data line is tested first, and then the address line detection is performed after the short/open circuit condition of the data line passes, so that the memory cell can be tested after the address line detection is completed. If all three processes pass the test, the DDR memory system is free from faults. If one step fails to detect, corresponding faults exist in hardware corresponding to the DDR memory. According to the scheme, DDR is detected in three aspects, the detection comprehensiveness is increased, and the detection reliability is greatly increased.
Referring to fig. 5, an embodiment of the present invention further provides a memory detection system, which includes:
the first detection module 501 sequentially writes one effective position and the other effective positions in the data lines into the DDR memory, and determines whether a short circuit or open circuit fault occurs in the data lines according to the consistency between the written data and the read data;
the second detection module 502 sequentially writes one effective position of the data lines high and the other effective positions low into the DDR memory, and judges whether the data lines have a short circuit or open circuit fault according to the consistency of the written data and the read data;
when it is determined that the data line has no short circuit or open circuit fault, the third detection module 503 writes preset data in the storage units corresponding to all available addresses of the DDR memory, and then determines whether the DDR memory has a hardware fault according to the consistency between the read back data and the preset data.
Optionally, as a possible implementation manner, the memory detection system in the embodiment of the present invention may further include:
the fourth detection module is used for sequentially writing data into the DDR memory when one effective position in the address lines is low and the other effective positions are high, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
and the fifth detection module is used for sequentially writing data into the DDR memory when one effective position in the address lines is high and the other effective positions are low, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data.
Optionally, as a possible implementation manner, the third detection module in the embodiment of the present invention may include:
the first detection unit writes 0 in all data bits of memory cells corresponding to all available addresses of the DDR memory, and then writes 1 in all data bits of memory cells corresponding to all available addresses of the DDR memory.
Optionally, as a possible implementation manner, the third detection module in the embodiment of the present invention may include:
and the second detection unit writes own memory address data into each storage unit of the DDR memory, and then rewrites complement data corresponding to the own memory address into each storage unit of the DDR memory.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
While the network diagram editor in the embodiment of the present invention is described above from the perspective of the modular functional entity, referring to fig. 6, the computer apparatus in the embodiment of the present invention is described below from the perspective of hardware processing:
the computer device 1 may include a memory 11, a processor 12 and an input output bus 13. The processor 11, when executing the computer program, implements the steps in the memory detection method embodiment shown in fig. 1, such as the steps 101 to 103 shown in fig. 1. Alternatively, the processor, when executing the computer program, implements the functions of each module or unit in the above-described device embodiments.
In some embodiments of the present invention, the processor is specifically configured to implement the following steps:
sequentially writing data into a DDR memory when one effective position in the data line is low and the other effective positions are high, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data;
sequentially enabling one effective position in the data lines to be high and the other effective positions to be low, writing data into the DDR memory, and judging whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
when the data line is judged to have no short circuit or open circuit fault, writing preset data into storage units corresponding to all available addresses of the DDR memory, and then judging whether the DDR memory has a hardware fault according to the consistency of the read data and the preset data.
Optionally, as a possible implementation manner, the processor may be further configured to implement the following steps:
sequentially writing data into a DDR memory when one effective position in address lines is low and the other effective positions are high, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
and sequentially writing data into the DDR memory when one effective position in the address lines is high and the other effective positions are low, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data.
Optionally, as a possible implementation manner, the processor may be further configured to implement the following steps:
and writing 0 into the data bits of the memory cells corresponding to all available addresses of the DDR memory, and then writing 1 into the data bits of the memory cells corresponding to all available addresses of the DDR memory.
Optionally, as a possible implementation manner, the processor may be further configured to implement the following steps:
writing own memory address data into each storage unit of the DDR memory, and then rewriting complement data corresponding to the own memory address into each storage unit of the DDR memory.
The memory 11 includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a hard disk, a multimedia card, a card type memory (e.g., SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, and the like. The memory 11 may in some embodiments be an internal storage unit of the computer device 1, for example a hard disk of the computer device 1. The memory 11 may also be an external storage device of the computer apparatus 1 in other embodiments, such as a plug-in hard disk provided on the computer apparatus 1, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory 11 may also include both an internal storage unit and an external storage device of the computer apparatus 1. The memory 11 may be used not only to store application software installed in the computer apparatus 1 and various types of data, such as codes of the computer program 01, but also to temporarily store data that has been output or is to be output.
The processor 12 may be a Central Processing Unit (CPU), controller, microcontroller, microprocessor or other data Processing chip in some embodiments, and is used for executing program codes stored in the memory 11 or Processing data, such as executing the computer program 01.
The input/output bus 13 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc.
Further, the computer apparatus may further include a wired or wireless network interface 14, and the network interface 14 may optionally include a wired interface and/or a wireless interface (such as a WI-FI interface, a bluetooth interface, etc.), which are generally used for establishing a communication connection between the computer apparatus 1 and other electronic devices.
Optionally, the computer device 1 may further include a user interface, the user interface may include a Display (Display), an input unit such as a Keyboard (Keyboard), and optionally, the user interface may further include a standard wired interface and a wireless interface. Alternatively, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch device, or the like. The display, which may also be referred to as a display screen or display unit, is suitable for displaying information processed in the computer device 1 and for displaying a visualized user interface.
Fig. 6 shows only the computer arrangement 1 with the components 11-14 and the computer program 01, it being understood by a person skilled in the art that the structure shown in fig. 6 does not constitute a limitation of the computer arrangement 1, but may comprise fewer or more components than shown, or a combination of certain components, or a different arrangement of components.
The present invention also provides a computer-readable storage medium having a computer program stored thereon, which when executed by a processor, performs the steps of:
sequentially writing data into a DDR memory when one effective position in the data line is low and the other effective positions are high, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data;
sequentially enabling one effective position in the data lines to be high and the other effective positions to be low, writing data into the DDR memory, and judging whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
when the data line is judged to have no short circuit or open circuit fault, writing preset data into storage units corresponding to all available addresses of the DDR memory, and then judging whether the DDR memory has a hardware fault according to the consistency of the read data and the preset data.
Optionally, as a possible implementation manner, the processor may be further configured to implement the following steps:
sequentially writing data into a DDR memory when one effective position in address lines is low and the other effective positions are high, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
and sequentially writing data into the DDR memory when one effective position in the address lines is high and the other effective positions are low, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data.
Optionally, as a possible implementation manner, the processor may be further configured to implement the following steps:
and writing 0 into the data bits of the memory cells corresponding to all available addresses of the DDR memory, and then writing 1 into the data bits of the memory cells corresponding to all available addresses of the DDR memory.
Optionally, as a possible implementation manner, the processor may be further configured to implement the following steps:
writing own memory address data into each storage unit of the DDR memory, and then rewriting complement data corresponding to the own memory address into each storage unit of the DDR memory.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A memory detection method is characterized by comprising the following steps:
sequentially writing data into a DDR memory when one effective position in the data line is low and the other effective positions are high, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data;
sequentially enabling one effective position in the data lines to be high and the other effective positions to be low, writing data into the DDR memory, and judging whether the data lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
when the data line is judged to have no short circuit or open circuit fault, writing preset data into storage units corresponding to all available addresses of the DDR memory, and then judging whether the DDR memory has a hardware fault according to the consistency of the read back data and the preset data.
2. The method as claimed in claim 1, wherein before writing the preset data into the memory cells corresponding to all available addresses of the DDR memory, the method further comprises:
sequentially writing data into a DDR memory when one effective position in address lines is low and the other effective positions are high, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
and sequentially writing data into the DDR memory when one effective position in the address lines is high and the other effective positions are low, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data.
3. The method according to claim 1 or 2, wherein writing preset data in the memory cells corresponding to all available addresses of the DDR memory comprises:
and writing 0 into data bits in the memory units corresponding to all available addresses of the DDR memory, and then writing 1 into the data bits in the memory units corresponding to all available addresses of the DDR memory.
4. The method according to claim 1 or 2, wherein writing preset data in the memory cells corresponding to all available addresses of the DDR memory comprises:
writing own memory address data into each storage unit of the DDR memory, and then rewriting complement data corresponding to the own memory address into each storage unit of the DDR memory.
5. A memory sensing system, comprising:
the first detection module is used for sequentially writing data into the DDR memory when an effective position in the data line is low and other positions are high, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data;
the second detection module is used for sequentially writing data into the DDR memory when one effective position in the data line is high and the other effective positions are low, and judging whether the data line has a short circuit or open circuit fault according to the consistency of the written data and the read data;
and the third detection module writes preset data into storage units corresponding to all available addresses of the DDR memory when the data line is judged to have no short circuit or open circuit fault, and then judges whether the DDR memory has hardware fault according to the consistency of the read back data and the preset data.
6. The system of claim 5, further comprising:
the fourth detection module is used for sequentially writing data into the DDR memory when one effective position in the address lines is low and the other effective positions are high, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data;
and the fifth detection module is used for sequentially writing data into the DDR memory when one effective position in the address lines is high and the other effective positions are low, and judging whether the address lines have short circuit or open circuit faults or not according to the consistency of the written data and the read data.
7. The system of claim 5 or 6, wherein the third detection module comprises:
and the first detection unit writes 0 in all the data bits of the storage units corresponding to all the available addresses of the DDR memory, and then writes 1 in all the data bits of the storage units corresponding to all the available addresses of the DDR memory.
8. The system of claim 5 or 6, wherein the third detection module comprises:
and the second detection unit writes own memory address data into each storage unit of the DDR memory, and then rewrites complement data corresponding to the own memory address into each storage unit of the DDR memory.
9. A computer arrangement, characterized in that the computer arrangement comprises a processor for implementing the steps of the method according to any one of claims 1 to 4 when executing a computer program stored in a memory.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program when executed by a processor implementing the steps of the method according to any one of claims 1 to 4.
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