CN111562998A - Memory diagnosis method and device for integrated circuit and storage medium - Google Patents
Memory diagnosis method and device for integrated circuit and storage medium Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
Abstract
The invention discloses a memory diagnosis method, a diagnosis device and a storage medium of an integrated circuit, which are characterized in that whether a data line has a fault or not is checked and judged by writing and reading a specific data value, whether the address line has the fault or not is checked and judged by writing and reading data into and from a storage unit with a specific address, whether the storage unit has the fault or not is checked and judged by writing and reading the data of the storage unit one by one, then specific reasons causing the bad fault and related signal lines are analyzed and displayed respectively, the memory chip on the integrated circuit is comprehensively diagnosed, and the fault display is carried out.
Description
Technical Field
The present invention relates to the field of integrated circuit testing technologies, and in particular, to a memory diagnosis method, a diagnosis device, and a storage medium for an integrated circuit.
Background
The memory chips and their accompanying circuitry in an integrated circuit are referred to as a memory subsystem, which is an important component of the integrated circuit. Integrated circuits are also typically equipped with a Central Processing Unit (CPU), and a memory subsystem is used to store the data needed by the CPU to execute program instructions. The memory subsystem provides the CPU with the ability to read and write data to the data storage unit, in particular.
The signal lines of the memory chip are mainly classified into two types, one type is a data line which is used for inputting or outputting a data value; one is an address line, which is used to specify the address number of the memory location of the data in the memory chip. For example, 32 address lines and 32 data lines of a common memory subsystem are provided, each address line and each data line can independently output 0 or 1, and 32 bit binary numbers formed by simultaneously outputting signals through the address lines represent the address of a storage unit of the memory chip; a 32-bit binary number composed of signals simultaneously output from 32 data lines represents one data value.
Because the memory chips and the signal lines on the integrated circuit are highly dense, defective products are easy to occur to the memory subsystem in the production and manufacturing process, common bad problems mainly include a data line short circuit problem or disconnection problem, an address line short circuit problem or disconnection problem, and a storage unit error in the memory chip, and the prior art cannot quickly and accurately detect the defective products and locate the specific bad problem reasons of the defective products and the corresponding signal lines.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
The invention mainly aims to provide a memory diagnosis method, a diagnosis device and a storage medium of an integrated circuit, aiming at solving the problems that the prior art can not quickly and accurately detect inferior-quality products and locate the specific bad problem causes of the inferior-quality products and corresponding signal lines.
In order to achieve the above object, the present invention provides a method for diagnosing a memory of an integrated circuit, including the steps of:
selecting any storage unit in the memory subsystem, writing first data into the selected storage unit and reading a first specific data value, writing second data into the selected storage unit and reading a second specific data value, checking the first specific data value and the second specific data value and judging whether a disconnection fault occurs in a data line;
when the data line is determined to have no disconnection fault, selecting any one storage unit in the memory subsystem, writing third data into the selected storage unit and reading a third specific data value, writing fourth data into the selected storage unit and reading a fourth specific data value, and judging whether the data line has a short-circuit fault according to the third specific data value and the fourth specific data value;
when the data line is determined to be normal, selecting a first storage unit of a first specific address in the memory subsystem to write a fifth specific data value, selecting a second storage unit of a second specific address in the memory subsystem to write a sixth specific data value, reading numerical values in the first storage unit and the second storage unit, and comparing the numerical values with the fifth specific data value and the sixth specific data value to judge whether a disconnection fault occurs to a current address line;
sequentially testing two adjacent address lines as a group, selecting a third storage unit of a third specific address in the memory subsystem to write a seventh specific data value, selecting a fourth storage unit of a fourth specific address in the memory subsystem to write an eighth specific data value, reading numerical values in the third storage unit and the fourth storage unit, and comparing the numerical values with the seventh specific data value and the eighth specific data value to judge whether the current address line has a short-circuit fault;
when the data line and the address line are determined to be normal, writing ninth specific data values into all storage units in the memory subsystem in sequence, and comparing the numerical values of all the storage units with the ninth specific data values to judge whether the storage units have faults or not; and sequentially writing tenth specific data values into all the storage units in the memory subsystem, and sequentially reading the numerical values of all the storage units to compare with the tenth specific data values to judge whether the storage units have faults or not.
Optionally, the method for diagnosing a memory of an integrated circuit, wherein the verifying the first specific data value and the second specific data value to determine whether a disconnection fault occurs in a data line specifically includes:
sequentially and correspondingly comparing the numerical values of each digit of the first specific data value and the second specific data value;
if the numerical values are the same, the corresponding data line is broken;
if the values are different, the corresponding data line is not broken.
Optionally, the memory diagnosis method of the integrated circuit, wherein the value of the odd-numbered bit in the third data is 0, and the value of the even-numbered bit is 1;
the value of the odd-numbered bit in the fourth data is 1, and the value of the even-numbered bit in the fourth data is 0.
Optionally, the method for diagnosing a memory of an integrated circuit, wherein the determining whether a short-circuit fault occurs in a data line according to the third specific data value and the fourth specific data value specifically includes:
if the value of a certain even number n in the third specific data value is 0, indicating that the nth data line corresponding to the even number n is short-circuited with one of the left and right adjacent data lines;
judging whether the nth data line corresponding to the even number n is short-circuited with the (n-1) th data line on the left or the (n + 1) th data line on the right;
if the value of a certain odd-numbered bit m in the fourth specific data value is 0, the m-th data line corresponding to the odd-numbered bit m is short-circuited with one data line adjacent to the m-th data line;
if the mth data line is the (n-1) th data line or the (n + 1) th data line, judging that the nth data line and the mth data line are in short circuit;
wherein m ═ n-1 or m ═ n + 1; n and m are positive integers.
Optionally, in the memory diagnostic method of an integrated circuit, the fifth specific data value and the sixth specific data value are not equal;
the reading of the numerical values in the first storage unit and the second storage unit, and the comparison of the fifth specific data value and the sixth specific data value determine whether the current address line has a disconnection fault, specifically including:
and if the numerical values read from the first storage unit and the second storage unit are simultaneously equal to the fifth specific data value or simultaneously equal to the sixth specific data value, the first storage unit and the second storage unit are the same storage unit, the current address line has disconnection fault, and all the address lines are tested in the same way.
Optionally, in the memory diagnostic method of an integrated circuit, the seventh specific data value and the eighth specific data value are not equal;
the reading of the numerical values in the third storage unit and the fourth storage unit, and the comparison of the seventh specific data value and the eighth specific data value determine whether the current address line has a short-circuit fault, specifically including:
and if the values read from the third storage unit and the fourth storage unit are simultaneously equal to the seventh specific data value or simultaneously equal to the eighth specific data value, the third storage unit and the fourth storage unit are the same storage unit, which indicates that two address lines in the current group have short-circuit faults, and the address lines in all the groups are tested in the same way.
Optionally, the method for diagnosing a memory of an integrated circuit, wherein the sequentially reading the values of all the storage units and comparing the values with the ninth specific data value to determine whether the storage unit has a fault specifically includes:
sequentially reading the numerical values of all the storage units, comparing the numerical values with the ninth specific data value, judging whether the numerical values read from the storage units are equal to the ninth specific data value or not, if so, judging that the current storage unit is normal, and if not, judging that the current storage unit has a fault;
the sequentially reading the numerical values of all the storage units and comparing the numerical values with the tenth specific data value to judge whether the storage units have faults specifically comprises:
and sequentially reading the numerical values of all the storage units, comparing the numerical values with the tenth specific data value, judging whether the numerical values read from the storage units are equal to the tenth specific data value or not, if so, judging that the current storage unit is normal, and if not, judging that the current storage unit has a fault.
Optionally, the method for diagnosing the memory of the integrated circuit, wherein the fault in the memory diagnosis includes: data line disconnection faults, data line short circuit faults, address line disconnection faults, address line short circuit faults, and memory cell faults;
and when any fault of the data line disconnection fault, the data line short-circuit fault, the address line disconnection fault, the address line short-circuit fault and the storage unit fault is diagnosed, displaying the current fault.
Further, to achieve the above object, the present invention also provides a diagnostic apparatus, wherein the diagnostic apparatus comprises: the memory diagnosis program of the integrated circuit realizes the steps of the memory diagnosis method of the integrated circuit when being executed by the processor.
In addition, in order to achieve the above object, the present invention further provides a storage medium, wherein the storage medium stores a memory diagnostic program of an integrated circuit, and the memory diagnostic program of the integrated circuit realizes the steps of the memory diagnostic method of the integrated circuit as described above when being executed by a processor.
According to the invention, any one storage unit in a memory subsystem is selected, first data is written into the selected storage unit and a first specific data value is read out, second data is written into the selected storage unit and a second specific data value is read out, and the first specific data value and the second specific data value are checked to judge whether a disconnection fault occurs to a data line; when the data line is determined to have no disconnection fault, selecting any one storage unit in the memory subsystem, writing third data into the selected storage unit and reading a third specific data value, writing fourth data into the selected storage unit and reading a fourth specific data value, and judging whether the data line has a short-circuit fault according to the third specific data value and the fourth specific data value; when the data line is determined to be normal, selecting a first storage unit of a first specific address in the memory subsystem to write a fifth specific data value, selecting a second storage unit of a second specific address in the memory subsystem to write a sixth specific data value, reading numerical values in the first storage unit and the second storage unit, and comparing the numerical values with the fifth specific data value and the sixth specific data value to judge whether a disconnection fault occurs to a current address line; sequentially testing two adjacent address lines as a group, selecting a third storage unit of a third specific address in the memory subsystem to write a seventh specific data value, selecting a fourth storage unit of a fourth specific address in the memory subsystem to write an eighth specific data value, reading numerical values in the third storage unit and the fourth storage unit, and comparing the numerical values with the seventh specific data value and the eighth specific data value to judge whether the current address line has a short-circuit fault; when the data line and the address line are determined to be normal, writing ninth specific data values into all storage units in the memory subsystem in sequence, and comparing the numerical values of all the storage units with the ninth specific data values to judge whether the storage units have faults or not; and sequentially writing tenth specific data values into all the storage units in the memory subsystem, and sequentially reading the numerical values of all the storage units to compare with the tenth specific data values to judge whether the storage units have faults or not. The invention checks and judges whether the data line has problems by writing and reading specific data values, checks and judges whether the address line has problems by writing and reading data into and from the memory unit with specific address, checks and judges whether the memory unit has problems by writing and reading data of the memory unit one by one, and then analyzes and displays specific reasons causing bad problems and related signal lines respectively, carries out comprehensive diagnosis on the memory chip on the integrated circuit, and carries out fault display.
Drawings
FIG. 1 is a flow chart of a memory diagnostic method of an integrated circuit according to a preferred embodiment of the present invention;
fig. 2 is a schematic diagram of the operation of a preferred embodiment of the breaking apparatus of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The short circuit problem is that a certain signal line is connected with another signal line, but the signal lines are not connected in design, so that signal interference is caused and mistransmission is caused; the short circuit can cause the signals output by the two related signal lines to influence each other, if the two signal lines output signals 1 and 0 (or 0 and 1) respectively during the short circuit, the signals actually received by the receiver can be mistakenly changed into 0 and 0 at the moment; when the short circuit occurs, the two signal lines output 0 or 1 simultaneously, and the signal actually received by the receiver is also 0 or 1 at the same time, but the signal is not influenced.
The disconnection problem is opposite, namely, one signal line is disconnected in the middle, so that the signal cannot be transmitted. Disconnection may cause the receiver to always receive a signal 0 (or always receive a signal 1) under the same circuit design, regardless of what signal is output by the signal line.
When a data line has a problem, the data value is transmitted in error, which is represented by writing a value into a memory cell with an arbitrary address, and then reading the value which is not equal to the value written before. When an address line has a problem, because the address value is transferred in error, data is written or read into or from a memory cell of a certain address, but data is actually written or read into or from a memory cell of another address, that is, a plurality of different address values point to the same memory cell.
A memory cell error, which is manifested as a certain bit or bits of data being read out from some memory cells to always be 0 or always be 1 or always be the opposite of the last written value.
First, in the memory subsystem of 32 data lines and 32 address lines as an example, 32 bits consisting of 1 and 0 represent signals of 32 data lines (or 32 address lines), such as 00000010010010001001001010100100, the leftmost bit represents the signal value of the 1 st signal line, the rightmost bit represents the signal value of the 32 th signal line, and the 32 data lines are arranged in the integrated circuit in the order of the 1 st to the 32 nd number, as well as the address lines.
As shown in fig. 1, the method for diagnosing the memory of the integrated circuit according to the preferred embodiment of the present invention includes the following steps:
step S10, selecting any one of the memory cells in the memory subsystem, writing the first data into the selected memory cell and reading the first specific data value, writing the second data into the selected memory cell and reading the second specific data value, and checking the first specific data value and the second specific data value to determine whether the data line has a disconnection fault.
Specifically, the numerical values of each digit of the first specific data value and the second specific data value are sequentially and correspondingly compared; if the numerical values are the same, the corresponding data line is broken; if the values are different, the corresponding data line is not broken.
When the data line is tested first, whether the address line has faults or not is also uncertain, but the fault is not important, because the memory unit is randomly selected to be written and read for testing at this time, and the problem of the address line does not influence the result of testing the data line. At the same time, whether the memory cell has a fault or not is also uncertain, and the step of repeatedly testing the data line by selecting a plurality of memory cells can be used, so that the problem that a certain memory cell has a fault to influence the test result is avoided.
Selecting a memory cell a1 (any memory cell) represented by an address 00000000000000000000000000000000 (the address is not specific and can be selected at will), writing data 00000000000000000000000000000000 (i.e., first data, where two signal lines output 0 or 1 at the same time when short circuit occurs, and the signal actually received by a receiver is also 0 or 1 at the same time, which seems to be unaffected, so that the written value can only be selected to be all 0 and all 1, avoiding the test interference caused by the short circuit problem of the data line), and then reading the data value D1 (where D1 represents a first specific data value) from the memory cell a 1; writing data 11111111111111111111111111111111 (i.e., the second data) into memory cell A1, and then reading the data value D2 (where D2 represents the second specific data value) from memory cell A1; normally D1 (first specific data value) and D2 (second specific data value) should be equal to 00000000000000000000000000000000 and 11111111111111111111111111111111, respectively. And sequentially comparing the numerical values of each digit of the D1 (first specific data value) and the D2 (second specific data value), wherein if the numerical values are the same, the corresponding data line has an open fault, and if the numerical values are different, the corresponding data line does not have the open fault.
For example, D1 (first specific data value) ═ 10000000000000000000000000000000 and D2 (second specific data value) ═ 11111111111111111111111111111111111111110 indicate that the 1 st data line and the 32 th data line have disconnection faults.
And after the test fails, ending the test process and displaying the faults found in the step.
Step S20, when it is determined that the data line has no disconnection fault, selecting any one of the memory cells in the memory subsystem, writing third data into the selected memory cell and reading a third specific data value, writing fourth data into the selected memory cell and reading a fourth specific data value, and determining whether the data line has a short-circuit fault according to the third specific data value and the fourth specific data value.
Wherein, the value of odd number bit in the third data is 0, and the value of even number bit is 1; the value of the odd-numbered bit in the fourth data is 1, and the value of the even-numbered bit in the fourth data is 0.
Specifically, if the value of some even number n in the third specific data value is 0, it indicates that the nth data line corresponding to the even number n is short-circuited with one of the data lines adjacent to the nth data line; judging whether the nth data line corresponding to the even number n is short-circuited with the (n-1) th data line on the left or the (n + 1) th data line on the right; if the value of a certain odd-numbered bit m in the fourth specific data value is 0, the m-th data line corresponding to the odd-numbered bit m is short-circuited with one data line adjacent to the m-th data line; if the mth data line is the (n-1) th data line or the (n + 1) th data line, judging that the nth data line and the mth data line are in short circuit; wherein m ═ n-1 or m ═ n + 1; n and m are positive integers.
When it is determined that the data line is not disconnected, selecting a memory cell a1 (any one of the memory cells) at an address 00000000000000000000000000000000 (the address is not specific and can be selected at will), writing data 01010101010101010101010101010101 (i.e., third data, the value of odd-numbered bits is 0, the value of even-numbered bits is 1, and the adjacent two-bit data is always 1 and 0 (or 0 and 1), so that the data becomes 0 and is exposed as long as there is a short circuit problem) into the memory cell a1, and reading the data value D1 (where D1 indicates a third specific data value) from the memory cell a 1; if a value of D1 (third specific data value) at an even bit n is 0, it indicates that the nth data line corresponding to the even bit n is shorted with one of the data lines adjacent thereto, but it is not determined whether the nth data line is shorted with the (n-1) th data line on the left or the (n + 1) th data line on the right. Continuing to write data 10101010101010101010101010101010 (i.e., the fourth data, the odd bits having a value of 1 and the even bits having a value of 0) into a1, and then reading the data from cell a1 having a value of D2 (where D2 represents the fourth specific data value); if the value of an odd bit m of D2 (the fourth specific data value) is 0, it indicates that the mth data line corresponding to the odd bit m is shorted with the next data line, and if the mth data line is the aforementioned nth-1 data line or the nth +1 data line, it is finally determined that the nth data line is shorted with the mth data line, where m is n-1 or m is n + 1.
And after the test fails, ending the test process and displaying the faults found in the step.
Step S30, when it is determined that the data line is normal, selecting the first storage unit of the first specific address in the memory subsystem to write a fifth specific data value, selecting the second storage unit of the second specific address in the memory subsystem to write a sixth specific data value, reading the values in the first storage unit and the second storage unit, and comparing the values with the fifth specific data value and the sixth specific data value to determine whether the disconnection fault occurs in the current address line.
Wherein the fifth particular data value and the sixth particular data value are not equal; specifically, if the values read from the first memory cell and the second memory cell are simultaneously equal to the fifth specific data value or simultaneously equal to the sixth specific data value, the first memory cell and the second memory cell are the same memory cell, the disconnection fault occurs on the current address line, and all the address lines are tested in the same manner.
When the memory unit is selected, only the value of the output signal of the tested address line or two address lines is required, and the output values of other address lines are not limited, so that the memory unit has a choice, and the influence of the fault of one memory unit on the test result is avoided.
When it is confirmed that the data line has no problem, starting from the 1 st address line, testing, selecting the memory cell a1 (i.e., the first memory cell of the first specific address) corresponding to the address 01111111111111111111111111111111 (i.e., the first specific address) composed of the 1 st address line outputting 0 and the remaining address lines outputting 1, and writing the data value D1 (where D1 represents the fifth specific data value) into the memory cell a1 (the first memory cell of the first specific address); then, selecting a memory cell a2 (i.e., the second memory cell of the second specific address) corresponding to an address 11111111111111111111111111111111 (i.e., the second specific address) composed of all address lines outputting 1, and writing a data value D2 (where D2 represents the sixth specific data value) which is not equal to D1 (the fifth specific data value) into the memory cell a2 (the second memory cell of the second specific address); then the values in memory cell a1 (the first memory cell of the first specific address) and memory cell a2 (the second memory cell of the second specific address) are read, respectively, and if their values are equal to both D1 (the fifth specific data value) or D2 (the sixth specific data value), it indicates that memory cell a1 (the first memory cell of the first specific address) and memory cell a2 (the second memory cell of the second specific address) are actually the same memory cell, i.e. the disconnection of the 1 st address line results in the 01111111111111111111111111111111 address and the 11111111111111111111111111111111 address pointing to the same memory cell (why there is no adjacent address line short, because if the 1 st address line and the 2 nd address line short, 01111111111111111111111111111111 actually becomes pointing to the 00111111111111111111111111111111 address, rather than to the 11111111111111111111111111111111 address). And the 2 nd address line is continuously tested in the same way until the 32 nd address line is tested.
Once the test fails, the test process is ended and the faults found in this step are displayed.
And step S40, taking two adjacent address lines as a group to sequentially test, selecting a third storage unit of a third specific address in the memory subsystem to write a seventh specific data value, selecting a fourth storage unit of a fourth specific address in the memory subsystem to write an eighth specific data value, reading numerical values in the third storage unit and the fourth storage unit, and comparing the numerical values with the seventh specific data value and the eighth specific data value to judge whether the current address line has a short-circuit fault.
Wherein the seventh particular data value and the eighth particular data value are not equal; specifically, if the values read from the third memory cell and the fourth memory cell are simultaneously equal to the seventh specific data value or simultaneously equal to the eighth specific data value, the third memory cell and the fourth memory cell are the same memory cell, which indicates that a short-circuit fault occurs in two address lines in the current group, and the address lines in all the groups are tested in the same manner.
Short circuits concern two address lines, so two adjacent address lines are used as a group for testing; starting a test from the (1, 2) th address line, selecting a memory cell a1 (i.e., the third memory cell of the third specific address) corresponding to an address 01111111111111111111111111111111 (i.e., the third specific address) in which 1 address line outputs 0, the other address line outputs 1, and the rest address lines also output 1, and writing a data value D1 (where D1 denotes a seventh specific data value) into a1 (the third memory cell of the third specific address); selecting a memory cell A2 (i.e., a fourth memory cell of a fourth specific address) corresponding to an address 00111111111111111111111111111111 (i.e., a fourth specific address) composed of two address lines outputting 0 and the remaining address lines outputting 1, and writing a data value D2 (where D2 represents an eighth specific data value) which is not equal to D1 (a seventh specific data value) into A2 (a fourth memory cell of a fourth specific address); then, the values in a1 (the third memory cell of the third specific address) and a2 (the fourth memory cell of the fourth specific address) are read respectively, and if the values are equal to D1 (the seventh specific data value) or D2 (the eighth specific data value), it indicates that a1 (the third memory cell of the third specific address) and a2 (the fourth memory cell of the fourth specific address) are actually the same memory cell, i.e. the 1 st address line and the 2 nd address line are shorted, which results in 01111111111111111111111111111111 address and 00111111111111111111111111111111 addresses pointing to the same memory cell. And the (2) th address line is tested continuously in the same way until the (31) th address line and the (3) th address line are tested continuously.
And once the test fails, ending the test process and displaying the faults found in the step.
Step S50, when the data line and the address line are determined to be normal, writing ninth specific data values into all storage units in the memory subsystem in sequence, and comparing the values of all the storage units read in sequence with the ninth specific data values to judge whether the storage units have faults or not; and sequentially writing tenth specific data values into all the storage units in the memory subsystem, and sequentially reading the numerical values of all the storage units to compare with the tenth specific data values to judge whether the storage units have faults or not.
Specifically, the numerical values of all the storage units are sequentially read and compared with the ninth specific data value, whether the numerical values read from the storage units are equal to the ninth specific data value or not is judged, if yes, the current storage unit is normal, and if not, the current storage unit fails; and sequentially reading the numerical values of all the storage units, comparing the numerical values with the tenth specific data value, judging whether the numerical values read from the storage units are equal to the tenth specific data value or not, if so, judging that the current storage unit is normal, and if not, judging that the current storage unit has a fault.
When the data line and the address line are confirmed to have no problem, the numerical values D1 are written into all the memory cells in sequence to be 00000000000000000000000000000000 (the numerical value D1 is marked to represent the ninth specific data value), then the numerical values are read in sequence to compare whether the numerical values are equal to D1 (the ninth specific data value), if the numerical values are not equal, the memory cells have the problem, the test process is ended, and the fault found in the step is displayed. Then, the values D2 are written into all the memory cells in sequence 11111111111111111111111111111111 (where D2 represents the tenth specific data value), and then the values are read in sequence to compare whether the values are equal to D2 (the tenth specific data value), if the values are not equal, the memory cell has a problem, the test process is ended, and the fault found in the step is displayed.
In the present invention, the fault in the memory diagnosis includes: data line disconnection faults, data line short circuit faults, address line disconnection faults, address line short circuit faults, and memory cell faults; and when any fault of the data line disconnection fault, the data line short-circuit fault, the address line disconnection fault, the address line short-circuit fault and the storage unit fault is diagnosed, displaying the current fault.
According to the corresponding change relationship between the signal output when the short circuit and the disconnection and the actually received signal, in combination with the fact that the data value read out from the same storage unit is equal to the data value written in last time under normal conditions, the invention verifies and judges whether the data line has problems or not by writing and reading the specific data value, verifies and judges whether the address line has problems or not by writing and reading the data into and from the storage unit with a specific address, verifies and judges whether the storage unit has problems or not by writing and reading the data of the storage unit one by one, and then analyzes and displays the specific reason causing the bad problems and the related signal line respectively.
Further, as shown in fig. 2, based on the memory diagnosis method of the integrated circuit, the present invention also provides a diagnosis device, which includes a processor 10, a memory 20 and a display 30. Fig. 2 shows only some of the components of the diagnostic device, but it is to be understood that not all of the shown components are required to be implemented, and that more or fewer components may be implemented instead.
The memory 20 may in some embodiments be an internal storage unit of the diagnostic device, such as a hard disk or a memory of the diagnostic device. The memory 20 may also be an external storage device of the diagnostic device in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like provided on the diagnostic device. Further, the memory 20 may also include both an internal storage unit and an external storage device of the diagnostic device. The memory 20 is used for storing application software installed in the diagnostic equipment and various types of data, such as program codes of the installed diagnostic equipment. The memory 20 may also be used to temporarily store data that has been output or is to be output. In one embodiment, the memory 20 stores an integrated circuit memory diagnostic program 40, and the integrated circuit memory diagnostic program 40 can be executed by the processor 10, so as to implement the integrated circuit memory diagnostic method of the present application.
The processor 10 may be, in some embodiments, a Central Processing Unit (CPU), a microprocessor or other data Processing chip, which is used for executing program codes stored in the memory 20 or Processing data, such as executing memory diagnosis methods of the integrated circuit.
The display 30 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch panel, or the like in some embodiments. The display 30 is used to display information at the diagnostic device and to display a visual user interface. The components 10-30 of the diagnostic device communicate with each other via a system bus.
In one embodiment, the following steps are implemented when the processor 10 executes the memory diagnostic program 40 of the integrated circuit in the memory 20:
selecting any storage unit in the memory subsystem, writing first data into the selected storage unit and reading a first specific data value, writing second data into the selected storage unit and reading a second specific data value, checking the first specific data value and the second specific data value and judging whether a disconnection fault occurs in a data line;
when the data line is determined to have no disconnection fault, selecting any one storage unit in the memory subsystem, writing third data into the selected storage unit and reading a third specific data value, writing fourth data into the selected storage unit and reading a fourth specific data value, and judging whether the data line has a short-circuit fault according to the third specific data value and the fourth specific data value;
when the data line is determined to be normal, selecting a first storage unit of a first specific address in the memory subsystem to write a fifth specific data value, selecting a second storage unit of a second specific address in the memory subsystem to write a sixth specific data value, reading numerical values in the first storage unit and the second storage unit, and comparing the numerical values with the fifth specific data value and the sixth specific data value to judge whether a disconnection fault occurs to a current address line;
sequentially testing two adjacent address lines as a group, selecting a third storage unit of a third specific address in the memory subsystem to write a seventh specific data value, selecting a fourth storage unit of a fourth specific address in the memory subsystem to write an eighth specific data value, reading numerical values in the third storage unit and the fourth storage unit, and comparing the numerical values with the seventh specific data value and the eighth specific data value to judge whether the current address line has a short-circuit fault;
when the data line and the address line are determined to be normal, writing ninth specific data values into all storage units in the memory subsystem in sequence, and comparing the numerical values of all the storage units with the ninth specific data values to judge whether the storage units have faults or not; and sequentially writing tenth specific data values into all the storage units in the memory subsystem, and sequentially reading the numerical values of all the storage units to compare with the tenth specific data values to judge whether the storage units have faults or not.
The verifying the first specific data value and the second specific data value to determine whether a disconnection fault occurs in the data line specifically includes:
sequentially and correspondingly comparing the numerical values of each digit of the first specific data value and the second specific data value;
if the numerical values are the same, the corresponding data line is broken;
if the values are different, the corresponding data line is not broken.
The value of the odd number bit in the third data is 0, and the value of the even number bit in the third data is 1;
the value of the odd-numbered bit in the fourth data is 1, and the value of the even-numbered bit in the fourth data is 0.
The determining whether a short-circuit fault occurs in the data line according to the third specific data value and the fourth specific data value specifically includes:
if the value of a certain even number n in the third specific data value is 0, indicating that the nth data line corresponding to the even number n is short-circuited with one of the left and right adjacent data lines;
judging whether the nth data line corresponding to the even number n is short-circuited with the (n-1) th data line on the left or the (n + 1) th data line on the right;
if the value of a certain odd-numbered bit m in the fourth specific data value is 0, the m-th data line corresponding to the odd-numbered bit m is short-circuited with one data line adjacent to the m-th data line;
if the mth data line is the (n-1) th data line or the (n + 1) th data line, judging that the nth data line and the mth data line are in short circuit;
wherein m ═ n-1 or m ═ n + 1; n and m are positive integers.
The fifth particular data value and the sixth particular data value are not equal;
the reading of the numerical values in the first storage unit and the second storage unit, and the comparison of the fifth specific data value and the sixth specific data value determine whether the current address line has a disconnection fault, specifically including:
and if the numerical values read from the first storage unit and the second storage unit are simultaneously equal to the fifth specific data value or simultaneously equal to the sixth specific data value, the first storage unit and the second storage unit are the same storage unit, the current address line has disconnection fault, and all the address lines are tested in the same way.
The seventh particular data value and the eighth particular data value are not equal;
the reading of the numerical values in the third storage unit and the fourth storage unit, and the comparison of the seventh specific data value and the eighth specific data value determine whether the current address line has a short-circuit fault, specifically including:
and if the values read from the third storage unit and the fourth storage unit are simultaneously equal to the seventh specific data value or simultaneously equal to the eighth specific data value, the third storage unit and the fourth storage unit are the same storage unit, which indicates that two address lines in the current group have short-circuit faults, and the address lines in all the groups are tested in the same way.
The sequentially reading the numerical values of all the storage units and comparing the numerical values with the ninth specific data value to judge whether the storage unit has a fault specifically comprises:
sequentially reading the numerical values of all the storage units, comparing the numerical values with the ninth specific data value, judging whether the numerical values read from the storage units are equal to the ninth specific data value or not, if so, judging that the current storage unit is normal, and if not, judging that the current storage unit has a fault;
the sequentially reading the numerical values of all the storage units and comparing the numerical values with the tenth specific data value to judge whether the storage units have faults specifically comprises:
and sequentially reading the numerical values of all the storage units, comparing the numerical values with the tenth specific data value, judging whether the numerical values read from the storage units are equal to the tenth specific data value or not, if so, judging that the current storage unit is normal, and if not, judging that the current storage unit has a fault.
The fault in the memory diagnosis includes: data line disconnection faults, data line short circuit faults, address line disconnection faults, address line short circuit faults, and memory cell faults;
and when any fault of the data line disconnection fault, the data line short-circuit fault, the address line disconnection fault, the address line short-circuit fault and the storage unit fault is diagnosed, displaying the current fault.
The present invention also provides a storage medium, wherein the storage medium stores a memory diagnostic program of an integrated circuit, and the memory diagnostic program of the integrated circuit implements the steps of the memory diagnostic method of the integrated circuit as described above when being executed by a processor.
In summary, the present invention provides a memory diagnosis method, a diagnosis device and a storage medium for an integrated circuit, the method includes: selecting any storage unit in the memory subsystem, writing first data into the selected storage unit and reading a first specific data value, writing second data into the selected storage unit and reading a second specific data value, checking the first specific data value and the second specific data value and judging whether a disconnection fault occurs in a data line; when the data line is determined to have no disconnection fault, selecting any one storage unit in the memory subsystem, writing third data into the selected storage unit and reading a third specific data value, writing fourth data into the selected storage unit and reading a fourth specific data value, and judging whether the data line has a short-circuit fault according to the third specific data value and the fourth specific data value; when the data line is determined to be normal, selecting a first storage unit of a first specific address in the memory subsystem to write a fifth specific data value, selecting a second storage unit of a second specific address in the memory subsystem to write a sixth specific data value, reading numerical values in the first storage unit and the second storage unit, and comparing the numerical values with the fifth specific data value and the sixth specific data value to judge whether a disconnection fault occurs to a current address line; sequentially testing two adjacent address lines as a group, selecting a third storage unit of a third specific address in the memory subsystem to write a seventh specific data value, selecting a fourth storage unit of a fourth specific address in the memory subsystem to write an eighth specific data value, reading numerical values in the third storage unit and the fourth storage unit, and comparing the numerical values with the seventh specific data value and the eighth specific data value to judge whether the current address line has a short-circuit fault; when the data line and the address line are determined to be normal, writing ninth specific data values into all storage units in the memory subsystem in sequence, and comparing the numerical values of all the storage units with the ninth specific data values to judge whether the storage units have faults or not; and sequentially writing tenth specific data values into all the storage units in the memory subsystem, and sequentially reading the numerical values of all the storage units to compare with the tenth specific data values to judge whether the storage units have faults or not. The invention checks and judges whether the data line has problems by writing and reading specific data values, checks and judges whether the address line has problems by writing and reading data into and from the memory unit with specific address, checks and judges whether the memory unit has problems by writing and reading data of the memory unit one by one, and then analyzes and displays specific reasons causing bad problems and related signal lines respectively, carries out comprehensive diagnosis on the memory chip on the integrated circuit, and carries out fault display.
Of course, it will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by a computer program instructing relevant hardware (such as a processor, a controller, etc.), and the program may be stored in a computer readable storage medium, and when executed, the program may include the processes of the above method embodiments. The storage medium may be a memory, a magnetic disk, an optical disk, etc.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A method for diagnosing memory in an integrated circuit, the method comprising:
selecting any storage unit in the memory subsystem, writing first data into the selected storage unit and reading a first specific data value, writing second data into the selected storage unit and reading a second specific data value, checking the first specific data value and the second specific data value and judging whether a disconnection fault occurs in a data line;
when the data line is determined to have no disconnection fault, selecting any one storage unit in the memory subsystem, writing third data into the selected storage unit and reading a third specific data value, writing fourth data into the selected storage unit and reading a fourth specific data value, and judging whether the data line has a short-circuit fault according to the third specific data value and the fourth specific data value;
when the data line is determined to be normal, selecting a first storage unit of a first specific address in the memory subsystem to write a fifth specific data value, selecting a second storage unit of a second specific address in the memory subsystem to write a sixth specific data value, reading numerical values in the first storage unit and the second storage unit, and comparing the numerical values with the fifth specific data value and the sixth specific data value to judge whether a disconnection fault occurs to a current address line;
sequentially testing two adjacent address lines as a group, selecting a third storage unit of a third specific address in the memory subsystem to write a seventh specific data value, selecting a fourth storage unit of a fourth specific address in the memory subsystem to write an eighth specific data value, reading numerical values in the third storage unit and the fourth storage unit, and comparing the numerical values with the seventh specific data value and the eighth specific data value to judge whether the current address line has a short-circuit fault;
when the data line and the address line are determined to be normal, writing ninth specific data values into all storage units in the memory subsystem in sequence, and comparing the numerical values of all the storage units with the ninth specific data values to judge whether the storage units have faults or not; and sequentially writing tenth specific data values into all the storage units in the memory subsystem, and sequentially reading the numerical values of all the storage units to compare with the tenth specific data values to judge whether the storage units have faults or not.
2. The method according to claim 1, wherein the verifying the first specific data value and the second specific data value to determine whether a disconnection fault occurs in the data line specifically comprises:
sequentially and correspondingly comparing the numerical values of each digit of the first specific data value and the second specific data value;
if the numerical values are the same, the corresponding data line is broken;
if the values are different, the corresponding data line is not broken.
3. The method of claim 1, wherein the third data has odd bits with a value of 0 and even bits with a value of 1;
the value of the odd-numbered bit in the fourth data is 1, and the value of the even-numbered bit in the fourth data is 0.
4. The method according to claim 3, wherein the determining whether the data line has a short-circuit fault according to the third specific data value and the fourth specific data value specifically comprises:
if the value of a certain even number n in the third specific data value is 0, indicating that the nth data line corresponding to the even number n is short-circuited with one of the left and right adjacent data lines;
judging whether the nth data line corresponding to the even number n is short-circuited with the (n-1) th data line on the left or the (n + 1) th data line on the right;
if the value of a certain odd-numbered bit m in the fourth specific data value is 0, the m-th data line corresponding to the odd-numbered bit m is short-circuited with one data line adjacent to the m-th data line;
if the mth data line is the (n-1) th data line or the (n + 1) th data line, judging that the nth data line and the mth data line are in short circuit;
wherein m ═ n-1 or m ═ n + 1; n and m are positive integers.
5. The method of claim 1, wherein the fifth specific data value and the sixth specific data value are not equal;
the reading of the numerical values in the first storage unit and the second storage unit, and the comparison of the fifth specific data value and the sixth specific data value determine whether the current address line has a disconnection fault, specifically including:
and if the numerical values read from the first storage unit and the second storage unit are simultaneously equal to the fifth specific data value or simultaneously equal to the sixth specific data value, the first storage unit and the second storage unit are the same storage unit, the current address line has disconnection fault, and all the address lines are tested in the same way.
6. The method of claim 1, wherein the seventh specific data value and the eighth specific data value are not equal;
the reading of the numerical values in the third storage unit and the fourth storage unit, and the comparison of the seventh specific data value and the eighth specific data value determine whether the current address line has a short-circuit fault, specifically including:
and if the values read from the third storage unit and the fourth storage unit are simultaneously equal to the seventh specific data value or simultaneously equal to the eighth specific data value, the third storage unit and the fourth storage unit are the same storage unit, which indicates that two address lines in the current group have short-circuit faults, and the address lines in all the groups are tested in the same way.
7. The method according to claim 1, wherein the comparing the values of all the memory cells read sequentially with the ninth specific data value to determine whether the memory cell has a fault includes:
sequentially reading the numerical values of all the storage units, comparing the numerical values with the ninth specific data value, judging whether the numerical values read from the storage units are equal to the ninth specific data value or not, if so, judging that the current storage unit is normal, and if not, judging that the current storage unit has a fault;
the sequentially reading the numerical values of all the storage units and comparing the numerical values with the tenth specific data value to judge whether the storage units have faults specifically comprises:
and sequentially reading the numerical values of all the storage units, comparing the numerical values with the tenth specific data value, judging whether the numerical values read from the storage units are equal to the tenth specific data value or not, if so, judging that the current storage unit is normal, and if not, judging that the current storage unit has a fault.
8. The method of claim 1, wherein the fault in the memory diagnosis comprises: data line disconnection faults, data line short circuit faults, address line disconnection faults, address line short circuit faults, and memory cell faults;
and when any fault of the data line disconnection fault, the data line short-circuit fault, the address line disconnection fault, the address line short-circuit fault and the storage unit fault is diagnosed, displaying the current fault.
9. A diagnostic apparatus, characterized in that the diagnostic apparatus comprises: a memory, a processor and a memory diagnostic program for an integrated circuit stored on the memory and operable on the processor, the memory diagnostic program for the integrated circuit implementing the steps of the memory diagnostic method for an integrated circuit as claimed in any one of claims 1 to 8 when executed by the processor.
10. A storage medium storing a memory diagnostic program for an integrated circuit, the memory diagnostic program for an integrated circuit implementing the steps of the memory diagnostic method for an integrated circuit according to any one of claims 1 to 8 when executed by a processor.
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