CN112822074A - Single-node reflective memory and reflective memory network fault detection method - Google Patents
Single-node reflective memory and reflective memory network fault detection method Download PDFInfo
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- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
Abstract
The invention relates to a single-node reflective memory and a reflective memory network fault detection method, which are technically characterized by comprising the following steps: the method comprises the steps that specific data are written into a data line, the data in the data line are read after data processing of the data line, and the data are compared with a set result, so that data line detection, address line detection and physical storage component detection are carried out to detect whether a single-node reflective memory has a fault or not; whether the reflective memory network has faults or not is detected through reflective memory network data transmission abnormity detection and reflective memory network node offline fault detection, single-node reflective memory faults and system reflective memory faults are quickly and simply diagnosed, and reliability of the reflective memory network can be improved.
Description
Technical Field
The invention belongs to the technical field of reflective memory fault diagnosis, and particularly relates to a single-node reflective memory and a reflective memory network fault detection method.
Background
The reflective memory network is a mature technology, and is widely applied to the application fields of semi-physical simulation, flight simulator, automatic monitoring system, engine test bed, radio station simulator, high-speed data acquisition, beyond-the-horizon radar, ship navigation high-speed data transmission and the like through development for many years.
The reflecting memory has a unique hardware structure, so that the real-time transmission problem of a large amount of data is simplified to the greatest extent. The system designer does not need to understand the responsible data transmission process, only carries out read-write operation locally, and the hardware automatically completes the data synchronization with other nodes in the reflective memory network. The mechanism makes data transmission simple and rapid, simplifies system design, and the transmission characteristic of high-speed data transmission makes the reflective memory technology have incomparable advantages in system networking and communication schemes. The reliability and correctness of data transmission are the precondition of the quality characteristic of the reflective memory, and because the hardware of the reflective memory is highly integrated and the transparency of the drive to users, the fault detection and the detection of the reflective memory stage are relatively lacked.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a single-node reflective memory and a reflective memory network fault detection method, which can be used for diagnosing single-node reflective memory faults and system reflective memory faults.
The technical problem to be solved by the invention is realized by adopting the following technical scheme:
a single-node reflective memory and a reflective memory network fault detection method comprises the following steps:
step 1, detecting a single-node reflective memory fault;
step 1.1, data line detection;
step 1.2, detecting an address line;
step 1.3, detecting a physical storage component;
step 2, detecting faults of the reflective memory network;
step 2.1, detecting the data transmission abnormity of the reflective memory network;
and 2.2, reflecting off-line fault detection of the memory network nodes.
Moreover, the specific implementation method of step 1.1 is as follows:
step 1.1.1: writing AAAAAAAA to data lines16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.2, otherwise, the data line is short-circuited;
step 1.1.2: writing CCCCCCCCCC to data lines16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.3, otherwise, the data line is short-circuited;
step 1.1.3: writing F0F0F0F0 to a data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.4, otherwise, the data line is short-circuited;
step 1.1.4: writing FF00FF00 to a data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.5, otherwise, the data line is short-circuited;
step 1.1.5: writing FFFF0000 to data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.6, otherwise, the data line is short-circuited;
step 1.1.6: writing AAAAAAAA to data lines16The data is read out from the data line, the written data and the read data are compared, if the written data and the read data are the same, the step 1.1.7 is carried out, otherwise, the data line is disconnected;
step 1.1.7: writing CCCCCCCCCC to data lines16The data is read out from the data line, the written data and the read data are compared, if the written data and the read data are the same, the step 1.1.8 is carried out, otherwise, the data line is disconnected;
step 1.1.8: writing F0F0F0F0 to a data line16The data is read out from the data line, the written data and the read data are compared, if the written data and the read data are the same, the step 1.1.9 is carried out, otherwise, the data line is disconnected;
step 1.1.9: writing FF00FF00 to a data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, proceeding to step 1.1.10, otherwise, the data line is open-circuited;
step 1.1.10: writing FFFF0000 to data line16And reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, the data line has no fault, otherwise, the data line is disconnected.
Moreover, the specific implementation method of the step 1.2 is as follows: writing the value of the address as data into a physical space corresponding to the address, and ensuring that the content of each position in the physical space is different; and sequentially overturning the value of each address line of the detection address to obtain an address, acquiring an address value from the overturning, judging whether the address value obtained by the overturning is the same as the value of the detection address, if so, indicating that each address line has a fault, otherwise, indicating that the address lines have no fault.
Moreover, the step 1.3 includes 0 mode detection of the memory chip; detecting a negative mode; detecting a checkerboard mode; detecting a checkerboard negation mode; detecting a bit flipping mode; detecting an address mode; and address inversion mode detection.
Moreover, the 0 mode detection of the memory chip is as follows: writing 00000000 to memory chip16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out negative mode detection, otherwise, failing the memory;
the negative mode detection of the memory chip is as follows: writing 11111111 into memory chip16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out checkerboard mode detection, otherwise, failing to store the data;
the checkerboard pattern detection of the memory chip is as follows: writing 55555555 to memory chip16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out check pattern detection, otherwise, the memory is in failure;
the check board negation mode detection of the memory chip is as follows: writing AAAAAAAA to memory chips16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out bit flip mode detection, otherwise, failing to store the data;
the bit flipping pattern detection of the memory chip is as follows: writing 1< (offset% 32) into the memory chip, reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, performing address mode detection, otherwise, failing to store the data;
the address mode detection of the memory chip is as follows: writing offset into the memory chip, reading the offset from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, performing address negation mode detection, otherwise, performing memory failure;
the address mode detection of the memory chip is as follows: writing (-offset) into the memory chip, reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, the memory has no fault, otherwise the memory has fault.
Moreover, said step 2.1 comprises:
step 2.1.1, selecting a node as an initial node in the reflective memory network;
step 2.1.2, the initial node divides the storage space into 1MB equal space;
step 2.1.3, filling data of a 1MB space by adopting a Monte Carlo algorithm;
step 2.1.4, generating CRC codes by using a CRC32 algorithm for the front data of 1MB, and filling the CRC codes into the tail part of the space of 1 MB;
step 2.1.5, the starting node sends a data updating notice to each node in the reflective memory network, and each node checks whether the data transmission is normal or not through CRC after receiving the data updating notice;
and 2.1.6, sequentially selecting initial nodes in the reflective memory network according to the network topology, and repeatedly executing the steps 1.2.1 to 1.2.5 until all the nodes in the reflective memory network are used as the initial nodes to finish the inspection.
Moreover, said step 2.2 comprises:
step 2.2.1, selecting a node as a main node in the reflective memory network;
step 2.2.2, the master node sets event data Bit0 to be 0, and broadcasts and sends the event data to each node in the network;
step 2.2.3, after receiving the broadcast information, each node feeds back the corresponding position of the event data to the main node as 1;
and 2.2.4, the master node receives and judges the feedback condition of each node, if the feedback condition is obtained, the node is proved to be online, and otherwise, the node is offline.
The invention has the advantages and positive effects that: the method comprises the steps that specific data are written into a data line, the data in the data line are read after data processing of the data line, and the data are compared with a set result, so that data line detection, address line detection and physical storage component detection are carried out to detect whether a single-node reflective memory has a fault or not; whether the reflective memory network has faults or not is detected through reflective memory network data transmission abnormity detection and reflective memory network node offline fault detection, single-node reflective memory faults and system reflective memory faults are quickly and simply diagnosed, and reliability of the reflective memory network can be improved.
Drawings
FIG. 1 is a flow chart of reflective memory single node memory fault detection in accordance with the present invention;
FIG. 2 is a block diagram of the reflective memory card hardware;
FIG. 3 is a schematic diagram of a reflective memory network ring network;
FIG. 4 is a schematic diagram of a reflective memory network star network.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
A single-node reflective memory and a reflective memory network fault detection method comprises the following steps:
step 1, single-node reflective memory fault detection. Fig. 1 shows a flow chart of reflective memory single-node memory failure detection.
As shown in fig. 2, the reflective Memory card is loaded with 128M or 256M SDRAM (Memory) for temporarily storing the shared data of each reflective Memory card in the network. The single-node reflective memory fault is mainly common to the memory faults, and therefore, the single-node reflective memory fault detection comprises data line detection, address line detection and physical storage unit detection.
And 1.1, detecting the data line. There are two types of errors in the data line connection, one is disconnection and one is mutual short circuit. The basic principle of detection is illustrated with two data lines, only 01 being written2Thereafter, the read data and the write data are compared to determine whether they are short-circuited or disconnected. When the address line is 32 bits, 101010101010101010101010101010102The pattern can detect data open circuit error between parity bits, and detect whether there is short circuit between two adjacent groups by the same method, which is 110011001100110011001100110011002The patterns, and so on, are 5 patterns in succession, as shown in table 1, and as long as the patterns are written and read in succession, the data line cross short failure can be detected.
Table 1 data line test mode table (32 bit)
| Mode(s) | Mode encoding |
| 1 | AAAAAAAA16 |
| 2 | CCCCCCCC16 |
| 3 | F0F0F0F016 |
| 4 | FF00FF0016 |
| 5 | FFFF000016 |
The method specifically comprises the following steps:
step 1.1.1: writing AAAAAAAA to data lines16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.2, otherwise, the data line is short-circuited;
step 1.1.2: writing CCCCCCCCCC to data lines16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.3, otherwise, the data line is short-circuited;
step 1.1.3: writing F0F0F0F0 to a data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.4, otherwise, the data line is short-circuited;
step 1.1.4: writing FF00FF00 to a data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.5, otherwise, the data line is short-circuited;
step 1.1.5: writing FFFF0000 to data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.6, otherwise, the data line is short-circuited;
step 1.1.6: writing AAAAAAAA to data lines16The data is read out from the data line, the written data and the read data are compared, if the written data and the read data are the same, the step 1.1.7 is carried out, otherwise, the data line is disconnected;
step 1.1.7: writing CCCCCCCCCC to data lines16And reading out data from the data line, comparing and writingData and read data, if the write data and the read data are the same, the step 1.1.8 is carried out, otherwise, the data line is disconnected;
step 1.1.8: writing F0F0F0F0 to a data line16The data is read out from the data line, the written data and the read data are compared, if the written data and the read data are the same, the step 1.1.9 is carried out, otherwise, the data line is disconnected;
step 1.1.9: writing FF00FF00 to a data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, proceeding to step 1.1.10, otherwise, the data line is open-circuited;
step 1.1.10: writing FFFF0000 to data line16And reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, the data line has no fault, otherwise, the data line is disconnected.
Meanwhile, in order to detect the floating bursts error, an operation of writing different values to different addresses can be inserted between writing and reading.
And 1.2, detecting an address line. A characteristic of an address line failure is that two different locations in the address space are mapped to the same physical location.
The method comprises the following specific steps:
writing the value of the address as data into a physical space corresponding to the address, and ensuring that the content of each position in the physical space is different; and sequentially overturning the value of each address line of the detection address to obtain an address, acquiring an address value from the overturning, judging whether the address value obtained by the overturning is the same as the value of the detection address, if so, indicating that each address line has a fault, otherwise, indicating that the address lines have no fault.
And 1.3, detecting the physical storage component. A common error of memory chips is bit flipping, thus for 0-mode detection of memory chips; detecting a negative mode; detecting a checkerboard mode; detecting a checkerboard negation mode; detecting a bit flipping mode; detecting an address mode; and address inversion mode detection.
The detection of the 0 mode of the memory chip is as follows: to the direction ofMemory chip write 0000000016Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out negative mode detection, otherwise, failing the memory;
the negative mode detection of the memory chip is as follows: writing 11111111 into memory chip16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out checkerboard mode detection, otherwise, failing to store the data;
the checkerboard pattern detection of the memory chip is as follows: writing 55555555 to memory chip16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out check pattern detection, otherwise, the memory is in failure;
the check board negation mode detection of the memory chip is as follows: writing AAAAAAAA to memory chips16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out bit flip mode detection, otherwise, failing to store the data;
the bit flipping pattern detection of the memory chip is as follows: writing 1< (offset% 32) into the memory chip, reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, performing address mode detection, otherwise, failing to store the data;
the address mode detection of the memory chip is as follows: writing offset into the memory chip, reading the offset from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, performing address negation mode detection, otherwise, performing memory failure;
the address mode detection of the memory chip is as follows: writing (-offset) into the memory chip, reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, the memory has no fault, otherwise the memory has fault.
And 2, detecting the fault of the reflective memory network. As shown in fig. 3, the reflective memory may be connected by fiber tails to form a ring network. As shown in fig. 4, the reflective memory may also form a star network through reflective memory switches. The star network is also a ring network in principle, and when the open circuit detection switch detects that the node is open circuit, the short circuit operation is carried out, the open circuit node is skipped, and the integrity of the whole network is maintained. Common faults of the reflective memory network include data transmission abnormal faults and node offline faults.
And 2.1, reflecting abnormal detection of the data transmission of the memory network.
The method specifically comprises the following steps:
step 2.1.1, selecting a node as an initial node in the reflective memory network;
step 2.1.2, the initial node divides the storage space into 1MB equal space;
step 2.1.3, filling data of a 1MB space by adopting a Monte Carlo algorithm;
step 2.1.4, generating CRC codes by using a CRC32 algorithm for the front data of 1MB, and filling the CRC codes into the tail part of the space of 1 MB;
step 2.1.5, the starting node sends a data updating notice to each node in the reflective memory network, and each node checks whether the data transmission is normal or not through CRC after receiving the data updating notice;
and 2.1.6, sequentially selecting initial nodes in the reflective memory network according to the network topology, and repeatedly executing the steps 1.2.1 to 1.2.5 until all the nodes in the reflective memory network are used as the initial nodes to finish the inspection.
And 2.2, reflecting off-line fault detection of the memory network nodes.
The method specifically comprises the following steps:
step 2.2.1, selecting a node as a main node in the reflective memory network;
step 2.2.2, the master node sets event data Bit0 to be 0, and broadcasts and sends the event data to each node in the network;
step 2.2.3, after receiving the broadcast information, each node feeds back the corresponding position of the event data to the main node as 1;
and 2.2.4, the master node receives and judges the feedback condition of each node, if the feedback condition is obtained, the node is proved to be online, and otherwise, the node is offline.
It should be emphasized that the embodiments described herein are illustrative rather than restrictive, and thus the present invention is not limited to the embodiments described in the detailed description, but also includes other embodiments that can be derived from the technical solutions of the present invention by those skilled in the art.
Claims (7)
1. A single-node reflective memory and a reflective memory network fault detection method are characterized in that: the method comprises the following steps:
step 1, detecting a single-node reflective memory fault;
step 1.1, data line detection;
step 1.2, detecting an address line;
step 1.3, detecting a physical storage component;
step 2, detecting faults of the reflective memory network;
step 2.1, detecting the data transmission abnormity of the reflective memory network;
and 2.2, reflecting off-line fault detection of the memory network nodes.
2. The method according to claim 1, wherein the method for detecting the fault of the single-node reflective memory and the reflective memory network comprises the following steps: the specific implementation method of the step 1.1 is as follows:
step 1.1.1: writing AAAAAAAA to data lines16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.2, otherwise, the data line is short-circuited;
step 1.1.2: writing CCCCCCCCCC to data lines16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.3, otherwise, the data line is short-circuited;
step 1.1.3: writing F0F0F0F0 to a data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.4, otherwise, the data line is short-circuited;
and (1).1.4: writing FF00FF00 to a data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.5, otherwise, the data line is short-circuited;
step 1.1.5: writing FFFF0000 to data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, performing the step 1.1.6, otherwise, the data line is short-circuited;
step 1.1.6: writing AAAAAAAA to data lines16The data is read out from the data line, the written data and the read data are compared, if the written data and the read data are the same, the step 1.1.7 is carried out, otherwise, the data line is disconnected;
step 1.1.7: writing CCCCCCCCCC to data lines16The data is read out from the data line, the written data and the read data are compared, if the written data and the read data are the same, the step 1.1.8 is carried out, otherwise, the data line is disconnected;
step 1.1.8: writing F0F0F0F0 to a data line16The data is read out from the data line, the written data and the read data are compared, if the written data and the read data are the same, the step 1.1.9 is carried out, otherwise, the data line is disconnected;
step 1.1.9: writing FF00FF00 to a data line16Reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, proceeding to step 1.1.10, otherwise, the data line is open-circuited;
step 1.1.10: writing FFFF0000 to data line16And reading data from the data line, comparing the written data with the read data, if the written data is the same as the read data, the data line has no fault, otherwise, the data line is disconnected.
3. The method according to claim 1, wherein the method for detecting the fault of the single-node reflective memory and the reflective memory network comprises the following steps: the specific implementation method of the step 1.2 is as follows: writing the value of the address as data into a physical space corresponding to the address, and ensuring that the content of each position in the physical space is different; and sequentially overturning the value of each address line of the detection address to obtain an address, acquiring an address value from the overturning, judging whether the address value obtained by the overturning is the same as the value of the detection address, if so, indicating that each address line has a fault, otherwise, indicating that the address lines have no fault.
4. The method according to claim 1, wherein the method for detecting the fault of the single-node reflective memory and the reflective memory network comprises the following steps: the step 1.3 comprises the 0 mode detection of the memory chip; detecting a negative mode; detecting a checkerboard mode; detecting a checkerboard negation mode; detecting a bit flipping mode; detecting an address mode; and address inversion mode detection.
5. The method according to claim 4, wherein the method for detecting the fault of the single-node reflective memory and the reflective memory network comprises the following steps:
the detection of the 0 mode of the memory chip is as follows: writing 00000000 to memory chip16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out negative mode detection, otherwise, failing the memory;
the negative mode detection of the memory chip is as follows: writing 11111111 into memory chip16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out checkerboard mode detection, otherwise, failing to store the data;
the checkerboard pattern detection of the memory chip is as follows: writing 55555555 to memory chip16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out check pattern detection, otherwise, the memory is in failure;
the check board negation mode detection of the memory chip is as follows: writing AAAAAAAA to memory chips16Reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, carrying out bit flip mode detection, otherwise, failing to store the data;
the bit flipping pattern detection of the memory chip is as follows: writing 1< (offset% 32) into the memory chip, reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, performing address mode detection, otherwise, failing to store the data;
the address mode detection of the memory chip is as follows: writing offset into the memory chip, reading the offset from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, performing address negation mode detection, otherwise, performing memory failure;
the address mode detection of the memory chip is as follows: writing (-offset) into the memory chip, reading from the memory chip, comparing the written data with the read data, if the written data is the same as the read data, the memory has no fault, otherwise the memory has fault.
6. The method according to claim 1, wherein the method for detecting the fault of the single-node reflective memory and the reflective memory network comprises the following steps: the step 2.1 comprises the following steps:
step 2.1.1, selecting a node as an initial node in the reflective memory network;
step 2.1.2, the initial node divides the storage space into 1MB equal space;
step 2.1.3, filling data of a 1MB space by adopting a Monte Carlo algorithm;
step 2.1.4, generating CRC codes by using a CRC32 algorithm for the front data of 1MB, and filling the CRC codes into the tail part of the space of 1 MB;
step 2.1.5, the starting node sends a data updating notice to each node in the reflective memory network, and each node checks whether the data transmission is normal or not through CRC after receiving the data updating notice;
and 2.1.6, sequentially selecting initial nodes in the reflective memory network according to the network topology, and repeatedly executing the steps 1.2.1 to 1.2.5 until all the nodes in the reflective memory network are used as the initial nodes to finish the inspection.
7. The method according to claim 1, wherein the method for detecting the fault of the single-node reflective memory and the reflective memory network comprises the following steps: said step 2.2 comprises:
step 2.2.1, selecting a node as a main node in the reflective memory network;
step 2.2.2, the master node sets event data Bit0 to be 0, and broadcasts and sends the event data to each node in the network;
step 2.2.3, after receiving the broadcast information, each node feeds back the corresponding position of the event data to the main node as 1;
and 2.2.4, the master node receives and judges the feedback condition of each node, if the feedback condition is obtained, the node is proved to be online, and otherwise, the node is offline.
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