JP2008171287A - Information equipment, connection inspection method, program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately and efficiently inspect whether or not a storage element substrate on which a storage element is mounted has been normally connected to a slot of a main board. <P>SOLUTION: This connection inspection method includes carrying out addressing in a first address line signal state that only one address line as the object of inspection is put in a selective signal level to write prescribed data in inspecting whether or not the wiring pattern of an RAM-DIMM2 and the pin of a DIMM slot 5 are put in an open state about the address line (S1), and carrying out addressing in a second signal state that the signal levels of all address lines are put in a signal level whose phase is opposite to that of the selective signal level to write data different from the prescribed data (S2), and carrying out addressing in the first signal state to read data (S3), and carrying out verify check (S4). This operation is repeated for the number of the address lines (S6 to S9). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a connection inspection technique for inspecting whether a memory element substrate on which a semiconductor memory element or the like is mounted is normally connected to a main board.

  2. Description of the Related Art Conventionally, in an image information device such as a digital copying machine, when performing a tangent check of a semiconductor memory element DIMM (Dual Inline Memory Module), for example, for an address line check, an address in the DIMM address space is 00... 0001, 00 .., 0010, 00... 0100, after data is written while being shifted bit by bit, a method of verify (Verify) is employed in which the written data is read and compared with the data before writing. The same applies to the data line check. Note that this tangential check is generally performed at the time of power-on in an information device such as an image information device.

The related prior art disclosed in Patent Document 1 will be described below.
This prior art intends to efficiently find a memory failure due to an incomplete connection of a data bus and an address bus. For this reason, in this conventional technique, a DSP (Digital Signal Processor) uses an N-bit address bus and an SDRAM (Synchronous Dynamic Random Access Memory) connected to the data bus as data for the same address as the address value. After writing, data at each address is read. Then, the read data corresponding to each address value is compared, and if they do not match, it is determined that the memory is defective due to the data bus. Next, the DSP writes all 0s at address 0, and further reads from address 0. Further, data is read from the specific address, all the data are ORed, and the address bit position of the memory defect caused by the address bus is specified from the finally calculated result.
JP 2004-334707 A

When the above-mentioned verify check is performed while changing the address to check the tangent of the semiconductor memory element, the memory space address is realized by a combination of CS (Chip Select) line, I / O buffer control line (DQM), and address line. Therefore, even if the address on the memory space is shifted bit by bit, only one of the plurality of address lines of the semiconductor memory element is not sequentially selected. Therefore, the conventional method is inaccurate. is there. Further, the number of address bits covering the memory space is larger than the sum of the number of each of the CS line, the input / output buffer control line (DQM), and the address line, so that the check becomes redundant and the inspection time becomes long. The reason why the sum of the numbers is reduced is that the number of address lines is reduced as a result of performing RAS side addressing and CAS side addressing in a time-sharing manner.
The present invention is intended to solve such a problem of the prior art. By inspecting each address line and the like one by one, it is possible to inspect accurately and reduce the number of inspections. It is an object of the present invention to provide a connection inspection technique that can be efficiently inspected.

According to a first aspect of the present invention, there is provided an information device in which a memory element substrate on which a memory element is mounted is electrically connected to a main board through a slot, and a connection between a wiring pattern provided on the memory element substrate and the slot It is characterized in that an inspection means for inspecting each address line whether or not the child is normally connected is provided.
According to a second aspect of the present invention, in an information device in which a memory element substrate on which a memory element is mounted is electrically connected to a main board via a slot, a wiring pattern provided on the memory element substrate is connected to the slot It is characterized by comprising inspection means for inspecting whether each child is normally connected or not for each input / output buffer control line.
According to a third aspect of the present invention, in an information device in which a memory element substrate on which a memory element is mounted is electrically connected to a main board via a slot, a wiring pattern provided on the memory element substrate is connected to the slot It is characterized by having an inspection means for inspecting by a verify check that writes and reads specific data for all data lines at the same time when inspecting whether the child is normally connected or not with respect to the data line. To do.

According to a fourth aspect of the present invention, in the information device according to the first, second, or third aspect, an abnormality display for displaying that there is an abnormality in the connection of the memory element substrate when a result of the inspection by the inspection means is different from an expected value Means are provided.
According to a fifth aspect of the present invention, in the information device according to the fourth aspect, the abnormality display means displays in which slot the storage element substrate connected is abnormal when the main board has a plurality of slots. It is characterized by making it.
The invention according to claim 6 is a wiring pattern provided on the storage element substrate in a connection inspection method for an information device in which a storage element substrate on which the storage element is mounted is electrically connected to a main board via a slot. And whether the connector of the slot is normally connected or not is checked for each address line and / or each input / output buffer control line.

According to a seventh aspect of the present invention, in the connection inspection method according to the sixth aspect, each of the address lines checks whether or not the wiring pattern provided on the storage element substrate and the connector of the slot are in an open state. The address lines are sequentially inspected, only one address line to be inspected is addressed in the first signal state in which the selection signal level is set, predetermined data is written, and the signal levels of all address lines are selected. Addressing is performed in a second signal state having a signal level opposite to the signal level, and data different from the predetermined data is written, and then addressing is performed in the first signal state to read the data and perform a verify check. It is characterized by inspecting by performing.
The invention according to claim 8 is the connection inspection method according to claim 6, wherein when the address line is inspected whether the wiring pattern provided on the memory element substrate and the adjacent connector of the slot are in a short state, Each address line is sequentially inspected, and only one address line to be inspected is addressed in the first signal state in which the selection signal level is set and predetermined data is written, and further, one address to be inspected is written. Only the address line adjacent to the line is addressed in a second signal state having a selection signal level different from that of the other address lines, and data different from the predetermined data is written, and then the first signal state In this case, the data is read out by performing address verification and a verification check is performed.

  According to a ninth aspect of the present invention, in the connection inspection method according to the sixth aspect, the input / output buffer control line determines whether or not the wiring pattern provided on the storage element substrate and the connector of the slot are normally connected. When a test is performed, a predetermined data is written to a predetermined address of a storage element selected in a signal state in which only one input / output buffer control line to be tested is set to a selection signal level, and the input / output written immediately before The operation of writing the data different from the written data at the predetermined address in the signal state in which only the input / output buffer control line adjacent to the buffer control line is at the selection signal level is repeated for the other input / output buffer control lines, By addressing each I / O buffer control line in the same way as writing, reading data and performing a verify check Characterized in that it 査.

According to a tenth aspect of the present invention, there is provided a wiring pattern provided on the storage element substrate in a connection inspection method for information equipment in which the storage element substrate on which the storage element is mounted is electrically connected to the main board via the slot. When the data line is inspected for proper connection between the connector and the slot connector, all the data lines are written at the same time, and data of a different signal level is written for all the data lines. It is characterized by inspecting by a verify check to be read.
According to an eleventh aspect of the present invention, in the connection inspection method according to the tenth aspect, two types of character code strings are used as write data, and a verification check is performed on each of the character code strings.
A twelfth aspect of the invention is a program for causing an information device to execute a connection test of the method according to any one of the sixth to eleventh aspects.
A thirteenth aspect of the invention is an information device-readable recording medium on which the program of the twelfth aspect is recorded.

  According to the present invention, it is inspected for each address line and each input / output buffer control line whether the wiring pattern provided on the memory element substrate and the connector of the slot are normally connected. Can be inspected accurately. In addition, the number of inspections is reduced, and inspection can be performed efficiently. In addition, since inspection is performed by a verify check in which specific data is written to and read from all data lines at the same time, the number of inspections is reduced and inspection can be performed efficiently.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the components, types, combinations, shapes, relative positions, and the like described in this embodiment are not merely intended to limit the scope of this description unless otherwise specified, but are merely illustrative examples. .
FIG. 1 is a block diagram showing a configuration of a main part of a main board of an information device and a RAM-DIMM as an embodiment of the present invention. As illustrated, the main board 1 is mounted with a CPU 3, a ROM 4, a DIMM slot 5, an operation display unit 6, and the like. The CPU 3 is connected to the ROM 4 via the system bus and the RAM-DIMM 2 which is the semiconductor memory element substrate via the DIMM slot 5. The CPU 3 operating according to the program has the RAM-DIMM 2, the ROM 4 and the operation display unit 6. Control. The program is stored in the ROM 4 or the like including the connection check program according to the present invention. Further, the operation display unit 6 is composed of, for example, an LCD (Liquid Crystal Display) and displays various types of information.
In this embodiment, the inspecting means described in the claims is realized by the CPU 3 and the ROM 4, and the abnormality display means is realized by the CPU 3, the ROM 4, the operation display unit 6, and the like.

FIG. 2 is a wiring diagram showing a wiring state in the RAM-DIMM 2. As shown in FIG. As shown in the figure, the RAM-DIMM 2 in this example is a 256-Mbyte DDR-SDRAM-DIMM in which eight 256-Mbit DDR-SDRAMs 20 to 27 are mounted on both sides of the board. In addition, as a wiring pattern for connecting the RAM-DIMM 2 to a pin of the DIMM slot 5 (corresponding to a connector described in claims), two CS (Chip Select) lines 11 and 13 AD (Address) lines 12 are provided. There are provided two BA (Bank Address) lines 13, eight DQM lines (input / output buffer control lines) 14, and 64 data lines 15. There are other power supply lines, GND lines, CLK lines, CKE lines, RAS lines, CAS lines, WE lines, etc., but they are omitted here.
The CS line 11 starts a command input cycle at the Low level, and the command is ignored at the High level. In the example shown in FIG. 2, one of the two CS lines selects a chip arranged on the upper side of the figure, and the other selects a chip arranged on the lower side. The BA line 13 is a signal for switching a bank in the DDR-SDRAMs 20 to 27. Addressing of the memory space is realized by selecting the BA line and selecting an address by using the AD line and giving a value on the RAS side and a value on the CAS side in a time-sharing manner. That is, the entire memory space is addressed with 28 bits (2 + 13 × 2). Further, the DQM line 14 controls the input / output buffer, turns the buffer on at a low level, and turns the buffer off at a high level.

Examples of the present invention will be described below.
[Example]
For the tangential inspection, an open check for checking whether the connection with the corresponding pin in the DIMM slot 5 is in an open state (a state in which the connection is not electrically connected), and a short state (electrically adjacent to the pin adjacent to the corresponding pin). There is a short check to check if the pin is short-circuited). First, the address line open check will be described with reference to the operation flow shown in FIG. In this embodiment, the connection inspection is performed, for example, when the power is turned on.
The signal state of the entire 13 AD lines 12 is expressed as AD [12-0]. First, only the AD line is selected so that the 0th bit (AD0) AD line becomes the inspection target (here, the selected signal level). AD [12-0] = 0000000000001b (b means that the numeric string on the left side is binary), and a predetermined data, for example, 5ah (h is the number) (It means that the numeric string on the left is hex) (step 1). Further, as AD [12-0] = 0000000000000b, data different from the data written earlier, such as 00h, is written in the corresponding address (step 2).

Then, data is read from the address corresponding to AD [12-0] = 0000000000001b (step 3), and if it is not the previously written data (5ah) (No in step 4), an open error is set (step 5). If the AD line of the check target bit is open, the first data (5ah) is written to the corresponding address of AD [12-0] = 0000000000000b and is overwritten when the next data (00h) is written. During verification, the data (00h) written for the second time is read out, and an error occurs because it is different from the expected value.
Next, the signal state is set to AD [12-0] = 00000000000010b (check target: AD line AD1) and the same check is performed (step 6), and AD [12-0] = 0.000000000000b (check target: AD2). A check is performed (step 7). Thereafter, only the AD line to be checked is set to the selection signal level “1”, and the AD lines to be checked are shifted one by one (step 8). If all 13 lines are checked (Yes in step 9). ) End check.

Next, the short check will be described according to the operation flow shown in FIG.
First, the signal state is AD [12-0] = 00000000000010b (check target: AD1), and predetermined data (for example, 5ah) is written to the corresponding address (step 11). Further, different data (for example, 00h) from the data written earlier is written in the corresponding addresses of AD [12-0] = 0000000000001b and AD [12-0] = 0000000000000100b in which the bits adjacent to the check target bit are set to the selection signal level ( Step 12).
Subsequently, data is read from the corresponding address of AD [12-0] = 00000000000010b (step 13), and if it is not the previously written data (5ah) (No in step 14), a short error is set (step 15). If the AD line to be checked is in a short state, the data (5ah) written to the corresponding address of AD [12-0] = 00000000000010b is AD [12-0] = 00000000000011b (when AD0 and AD1 are short) or Write to the corresponding address of AD [12-0] = 000000000000110 (when AD1 and AD2 are short) or AD [12-0] = 00000000000011b (when AD0, AD1, and AD2 are short) and the next data (00h) Since the same address is overwritten when the data is written, the data (00h) written next to the check target bit is read during verification, and an error occurs because it is different from the expected value.
Thereafter, the AD lines are shifted one by one in the same way as in the open check (step 16), and if all 13 lines are checked (Yes in step 17), the process ends.
Note that AD [12-0] = 0000000000001b and AD [12-0] = 1000000000000000b, which do not have both neighbors, write data (00h) only to the adjacent neighbor.
When there are a plurality of slots, the above-described open check and short check are performed for each slot.

The open check and short check of the DQM line 14 are the same method. Hereinafter, the connection check of the DQM line 14 will be described according to the operation flow shown in FIG. Here, the entire signal state of the eight DQM lines 14 is expressed as DQM [7-0].
First, the signal state is set to DQM [7-0] = 1111110b (check target: DQM0), and predetermined data (for example, 11h) is written to a predetermined address in the DDR-SDRAM chip connected to the check target DQM line (step 21). . Further, as DQM [7-0] = 1111101b, data (for example, 22h) different from the data originally written is written at the same address as when writing to the DDR-SDRAM chip to be checked (step 22). In this way, different data is written to each DDR-SDRAM chip connected to each DQM line (step 23).

Next, the first DQM line is read from the same address as at the time of writing (step 24), and if it is not previously written data (No in step 25), the DQM line at that time is regarded as a connection error (step 26). . If the DQM line is open, the input buffer is always on (ON) at the time of writing, so that data is written to the DDR-SDRAM chip of the opened DQM line at the time of writing other DQM lines. . As a result, an error occurs because the output of the DDR-SDRAM chip connected to the open DQM line is different from the expected value during verification. In addition, the same data is written in each DDR-SDRAM chip connected to the shorted DQM line, and an error occurs because it is different from the expected value during verification.
Thereafter, the inspection is performed by shifting the DQM lines one by one (step 27), and if all the eight lines are checked (Yes in step 28), the process ends.
At the time of the short check, the same data is written to each DDR-SDRAM chip connected to the shorted DQM line, and at the time of verification, a short error occurs because it differs from the expected value.
When there are a plurality of slots, such an open check and a short check are performed for each slot.

Next, a tangent check on the data line will be described. Here, the signal state of the entire 64 data lines is expressed as data [63-0].
First, data [63-0] = 555555555555555h is written to a predetermined address to perform a verify check. Further, data [63-0] = aaaaaaaaaaaaaaaaaah is written to the same address, and a verify check is performed. If these two verification check results are not as expected, an error is assumed. The data value is a bit value different from both sides on all data lines (that is, one of the two types of data is 0 on the odd-numbered data line from the lower side and 1 on the even-numbered data line). The other is the opposite, so that if the bit value is the same as both neighbors, it is shorted, and if the data line is always 0, it is open. The reason for checking with two types of data is that in the case of open check, one type cannot be surely checked.
If there are multiple slots, such a check is performed for each slot.

As described above, in the information apparatus of this embodiment, since each signal line is inspected one by one with certainty, the quality of the information apparatus can be improved. Further, in the information device of this embodiment, the total number of lines of 25 CS lines, 8 DQM lines and 15 address lines (including 2 BA lines) is more than 25 address bits for realizing the memory space. The number of books is smaller, and the tangent check of the data requires a smaller number of inspections by using specific data, so the check time is shortened.
In this embodiment, when the CPU 3 determines that there is a connection error through the connection check, the CPU 3 displays on the operation display unit 6 that there is an abnormality in the RAM-DIMM connection. Thereby, the user can easily know the connection failure of the RAM-DIMM. If there are a plurality of DIMM slots 5, the DIMM slot 5 connected to the RAM-DIMM 2 in which a connection error has occurred is clearly displayed and displayed on the operation display unit 6. Thereby, the user can easily know the RAM-DIMM with poor connection.

  Although the semiconductor element substrate connection inspection method of the present invention has been described with respect to one embodiment, the main board 1 includes a RAM, and an information device having the main board 1 drives a hard disk storage device or a removable recording medium. A digital copy in which a program programmed according to the version upgrade method described above is recorded on a detachable recording medium, and the semiconductor element substrate connection inspection according to the present invention has not been performed so far. The semiconductor element substrate connection according to the present invention is also applied to such information equipment by mounting it on information equipment such as a computer or a personal computer, or by transferring such a program to such information equipment via a network. Inspection can be performed.

It is a block diagram which shows the structure of the main board main part, etc. of information equipment as one Embodiment of this invention. It is a wiring diagram which shows the wiring condition in RAM-DIMM as one Embodiment of this invention. It is a flowchart which shows the operation | movement flow of the open check of an address line as one Example of this invention. It is a flowchart which shows the operation | movement flow of a short check of an address line as one Example of this invention. It is a flowchart which shows the operation | movement flow of the open check of a DQM line as one Example of this invention.

Explanation of symbols

  1 Main board, 2 RAM-DIMM, 3 CPU, 5 DIMM slot, 6 Operation display, 11 CS line, 12 AD line, 13 BA line, 14 DQM line, 15 data line, 20-27 DDR-SDRAM

Claims (13)

  In an information device in which a storage element substrate on which a storage element is mounted is electrically connected to a main board via a slot, a wiring pattern provided on the storage element substrate and a connector of the slot are normally connected An information device comprising inspection means for inspecting whether each address line is present or not.   In an information device in which a storage element substrate on which a storage element is mounted is electrically connected to a main board via a slot, a wiring pattern provided on the storage element substrate and a connector of the slot are normally connected An information device comprising inspection means for inspecting whether each input / output buffer control line is present or not.   In an information device in which a storage element substrate on which a storage element is mounted is electrically connected to a main board via a slot, a wiring pattern provided on the storage element substrate and a connector of the slot are normally connected An information device comprising inspection means for inspecting a data line by a verify check for reading and writing specific data for all data lines at a time when inspecting whether or not the data line is present.   4. The information apparatus according to claim 1, further comprising an abnormality display unit that displays that there is an abnormality in the connection of the storage element substrate when a result of the inspection by the inspection unit is different from an expected value. Information equipment.   5. The information device according to claim 4, wherein the abnormality display means displays a memory element substrate connected to which slot is abnormal when the main board has a plurality of slots. machine.   In a connection inspection method for an information device in which a memory element substrate on which a memory element is mounted is electrically connected to a main board through a slot, a wiring pattern provided on the memory element substrate and a connector of the slot A connection inspection method characterized by inspecting each address line and / or each input / output buffer control line for normal connection.   7. The connection inspection method according to claim 6, wherein when the address line is inspected to determine whether or not the wiring pattern provided on the storage element substrate and the connector of the slot are in an open state, the address lines are sequentially inspected. Then, a predetermined data is written by addressing in a first signal state in which only one address line to be inspected is set to the selection signal level, and the signal levels of all the address lines are signals having a phase opposite to the selection signal level. A test is performed by writing data different from the predetermined data by addressing in the second signal state at the level, and then performing a verify check by reading the data by addressing in the first signal state. Connection inspection method.   7. The connection inspection method according to claim 6, wherein when the address line is inspected whether or not the wiring pattern provided on the storage element substrate and the adjacent connector of the slot are in a short state, each address line is sequentially inspected. Then, addressing is performed in the first signal state in which only one address line to be inspected is set to the selection signal level and predetermined data is written, and only address lines adjacent to the one address line to be inspected are written. Address check in a second signal state having a selection signal level different from that of the other address lines to write data different from the predetermined data, and then address the first signal state to read the data and perform a verify check A connection inspection method characterized by inspecting by performing.   7. The connection inspection method according to claim 6, wherein when the input / output buffer control line is inspected as to whether or not the wiring pattern provided on the storage element substrate and the connector of the slot are normally connected. A predetermined data is written to a predetermined address of a selected storage element in a signal state in which only one input / output buffer control line is set to a selection signal level, and the input / output adjacent to the input / output buffer control line written immediately before is written. In the signal state where only the buffer control line is at the selection signal level, the operation of writing data different from the written data to the predetermined address is repeated for the other input / output buffer control lines, and then for each input / output buffer control line It is characterized in that it is inspected by addressing in the same way as writing and reading the data and performing a verify check. Connection inspection method.   In a connection inspection method for an information device in which a memory element substrate on which a memory element is mounted is electrically connected to a main board through a slot, a wiring pattern provided on the memory element substrate and a connector of the slot When inspecting data lines to determine whether they are properly connected, all data lines should be inspected at the same time using a verify check that reads and writes data at a different signal level from both adjacent lines. A connection inspection method characterized by.   11. The connection inspection method according to claim 10, wherein two types of character code strings are used as write data, and each of them is inspected by performing a verify check.   A program for causing an information device to execute a connection test according to the method of any one of claims 6 to 11.   An information device-readable recording medium on which the program according to claim 12 is recorded.

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