CN117594107A

CN117594107A - Test method and test circuit for detecting memory faults

Info

Publication number: CN117594107A
Application number: CN202410072219.6A
Authority: CN
Inventors: 刘筱彧
Original assignee: Anhui University; Nexchip Semiconductor Corp
Current assignee: Anhui University; Nexchip Semiconductor Corp
Priority date: 2024-01-18
Filing date: 2024-01-18
Publication date: 2024-02-23
Anticipated expiration: 2044-01-18
Also published as: CN117594107B

Abstract

The application discloses a test method and a test circuit for detecting a memory failure. The testing method comprises the following steps of executing the following multiple read-write operations on the storage space to be tested of the memory: performing write 0 operation in address descending order or address ascending order, performing read 0 operation and write 1 operation in address descending order, performing read 1 operation, write 0 operation, read 0 operation and write 1 operation for a plurality of times in address ascending order, performing read 1 operation, write 0 operation and read 0 operation in address ascending order, performing read 0 operation, write 1 operation, read 1 operation and write 0 operation for a plurality of times in address ascending order, and performing read 0 operation in address ascending order; and comparing the data read in the multiple read-write operations with expected data to determine whether the address in the storage space to be tested has faults. The test method realizes the improvement of the fault detection coverage rate.

Description

Test method and test circuit for detecting memory faults

Technical Field

The present invention relates to the field of device testing technologies, and in particular, to a testing method and a testing circuit for detecting a memory failure.

Background

As integrated circuit process sizes become smaller, more new types of failures occur in memory, including static link failures. According to the past memory test results in the industry, the method shows that: static link failures in memory cannot be ignored in processes of 40 nm and below. Thus, a test method for detecting a memory failure is required to be able to detect a static link failure as well.

Currently, the industrial detection of static link failure generally adopts a traveling methodMarch LR in (March), the test method is specifically described as:(w 0); ∈ (r 0, w 1); ∈ (r 1, w0, r0, w 1); ∈ (r 1, w 0); ∈ (r 0, w1, r1, w 0); and ∈r0, namely performing fault detection by performing the following operations on the storage space to be tested of the memory: 1) Performing write 0 operation according to the ascending order or the descending order of the addresses; 2) Performing a read 0 operation and a write 1 operation in descending order of addresses; 3) Performing a read 1 operation, a write 0 operation, a read 0 operation and a write 1 operation according to the ascending order of addresses; 4) Performing a read 1 operation and a write 0 operation according to the ascending order of addresses; 5) Performing a read 0 operation, a write 1 operation, a read 1 operation and a write 0 operation according to the ascending order of addresses; 6) And performing read 0 operation according to the ascending order of the addresses.

The March LR test method can detect all static link faults possibly encountered in reality, has good coverage rate on static non-link faults, can detect state faults, conversion faults, read damage faults, state coupling faults, coupling interference read faults, coupling interference reverse state write faults, coupling conversion faults, coupling read damage faults and coupling error read faults, and has no capability on write interference faults, deceptive read damage faults, coupling write damage faults and coupling deceptive read damage faults commonly encountered in industry.

Disclosure of Invention

In view of the foregoing, an object of the present application is to provide a test method and a test circuit for detecting a memory failure, which achieve an improvement in failure detection coverage by improving the test method of March LR.

According to a first aspect of the present invention, there is provided a test method for detecting a memory failure, comprising:

performing multiple read-write operations on a memory space to be tested of the memory;

comparing the data read in the multiple read-write operations with expected data to determine whether addresses in the storage space to be tested have faults or not;

wherein, the multiple read-write operations include:

a first write operation of performing a write 0 operation in descending address order or ascending address order;

the first read-write operation, the read 0 operation and the write 1 operation are carried out according to the descending order of the addresses;

performing a second read-write operation, namely performing multiple read 1 operations, write 0 operations, read 0 operations and write 1 operations according to the ascending order of addresses;

performing a read 1 operation, a write 0 operation and at least one read 0 operation according to the ascending order of addresses;

fourth read-write operation, performing multiple read 0 operations, write 1 operations, multiple read 1 operations and write 0 operations according to the ascending order of addresses;

and performing a first read operation, namely performing a read 0 operation according to the ascending order of addresses.

Optionally, the test method further comprises: and outputting the address and outputting the identification of the read operation for reading the data under the condition that the data read by the address in the storage space to be tested is inconsistent with the expected data.

Optionally, in the case that an address in the storage space to be tested has a spoofed read failure or a coupled spoofed read failure, the identification includes any one of the following: the identification of the first reading 0 operation in the fourth reading and writing operation, the identification of the second reading 1 operation in the fourth reading and writing operation and the identification of the second reading 1 operation in the second reading and writing operation.

Optionally, the coupling spoofing read destroys the address of the attacking cell higher than the address of the victim cell in the fault.

Optionally, the first write operation performs a write 0 operation in descending address order and the write 0 operation is repeated a plurality of times;

repeating the writing 1 operation of the first reading and writing operation for a plurality of times;

repeating the writing 0 operation of the third reading and writing operation for a plurality of times;

and repeating the writing 1 operation of the fourth reading and writing operation for a plurality of times.

Optionally, in a case that an address in the storage space to be tested has a write disturbance fault or a coupled write destruction fault, the identification includes any one of the following: the identification of the read 0 operation in the first read-write operation, the identification of the read 0 operation in the third read-write operation, the identification of the first read 1 operation in the second read-write operation, and the identification of the first read 1 operation in the fourth read-write operation.

Optionally, the coupled write destroys the address of the attacking cell higher than the address of the victim cell in the fault.

Optionally, the write 0 operation in the first write operation is performed once;

the reading 0 operation and the writing 1 operation in the first reading and writing operation are respectively carried out once;

the write 0 operation, the read 0 operation and the write 1 operation in the second read-write operation are respectively performed once, and the read 1 operation is performed twice;

the read 1 operation, the write 0 operation and the read 0 operation in the third read-write operation are respectively performed once;

the writing 1 operation and the writing 0 operation in the fourth reading and writing operation are respectively performed once, and the reading 0 operation and the reading 1 operation are respectively performed twice;

the read 0 operation in the first read operation is performed once.

According to a second aspect of the present invention, there is provided a test circuit for implementing any one of the test methods described in the first aspect, comprising:

an address generation unit for generating an address of the memory cell to be tested;

the data generation unit is used for generating data which is indicated by the address and needs to be written into the storage unit to be tested;

the control signal generation unit is used for generating a control signal to control the reading operation in the multiple times of reading and writing operations on the storage unit to be tested indicated by the address or the writing operation of the data in the multiple times of reading and writing operations on the storage unit to be tested indicated by the address;

And the comparison unit is used for comparing the data read in the multiple read-write operations with expected data to determine whether the address in the storage space to be tested has faults or not.

Optionally, the test circuit further comprises:

and an output unit configured to output the address and output an identification of a read operation for reading the data, in a case where the comparison unit compares the data read from the memory cell to be tested indicated by the address with desired data to obtain an inconsistent result.

The unexpected technical effect of this application is:

according to the test method of the embodiment of the invention, the existing test method March LR is improved, wherein the second read-write operation is obtained by adding at least one read-1 operation before the write-0 operation, the third read-write operation is obtained by adding at least one read-0 operation after the write-0 operation, and the fourth read-write operation is obtained by adding at least one read-0 operation before the write-1 operation and adding at least one read-1 operation between the write-1 operation and the write-0 operation. Compared with the prior test method March LR, the improved test method has the advantages that the detection functions of the deceptive read damage faults and the coupling deceptive read damage faults are increased.

Further, in the improved method, the first write operation is performed in descending order of address, the write 0 operation is repeatedly performed for a plurality of times, the write 1 operation of the first read-write operation is repeatedly performed for a plurality of times, the write 0 operation of the third read-write operation is repeatedly performed for a plurality of times, and the write 1 operation of the fourth read-write operation is repeatedly performed for a plurality of times, so that the original detection function is not affected, the detection functions of write interference faults and coupling write failure faults are added, and the detection of static link faults and the detection of all static non-link faults commonly encountered are covered.

Further, in the testing method of the embodiment of the invention, under the condition that the data read by an address in the storage space to be tested is inconsistent with the expected data, the address is output and the identification of the reading operation for reading the data is output, so that a user only needs to analyze the output data, wherein the output address is convenient for the user to directly determine which storage unit in the storage space to be tested has a fault, and the output identification is convenient for the user to analyze the type of the fault.

Drawings

The foregoing and other objects, features and advantages of the application will be more apparent from the following description of embodiments of the application with reference to the accompanying drawings in which:

FIG. 1 illustrates two exemplary independent coupling faults and one link fault formed by the two;

FIG. 2 is a flow chart of a test method for detecting memory failures according to an embodiment of the present application;

FIG. 3 illustrates the sensitized state and test state of a memory cell during execution of a failed March element sequence according to an embodiment of the present application;

FIG. 4 is a flow chart of another test method for detecting memory failures provided by an embodiment of the present application;

FIG. 5 (a) is a timing diagram illustrating the execution of a first step in another test method according to an embodiment of the present application;

FIG. 5 (b) is a timing diagram illustrating the execution of the second step in another test method according to an embodiment of the present application;

FIG. 5 (c) is a timing diagram illustrating the execution of a third step in another test method according to an embodiment of the present application;

FIG. 5 (d) is a timing diagram illustrating the execution of the fourth step in another test method according to the embodiment of the present application;

FIG. 5 (e) is a timing diagram illustrating the execution of a fifth step in another test method according to an embodiment of the present application;

FIG. 5 (f) is a timing diagram illustrating the execution of a sixth step in another test method according to an embodiment of the present application;

FIG. 6 illustrates another test method vs. fault primitive provided in accordance with an embodiment of the present application <1;0w0//->A timing diagram describing fault detection;

FIG. 7 illustrates another test method vs. fault primitive provided in accordance with an embodiment of the present application<0;1w1//->A timing diagram describing fault detection;

FIG. 8 illustrates a circuit diagram of a test circuit for detecting memory failures provided in accordance with another embodiment of the present application;

fig. 9 shows a circuit diagram of another test circuit for detecting memory failures provided in accordance with another embodiment of the present application.

Detailed Description

The present application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The present application may be presented in various forms, some examples of which are described below.

Currently, the test methods of memory failures used by enterprises are Scan (Scan), checkerboard (chekerberoard), such as Scan0 and Scan1, and March, such as CKBD and ICKBD, and March c+ which can only detect static unlink failures, but as integrated circuit process sizes become smaller, more new failures of memories, such as Link Failures (LF) and dynamic failures, are also generated, and the like, wherein the link failures cannot be ignored in processes of 40 nm and below as the memory test results of the past in the industry indicate that the test methods for detecting memory failures are desired to be able to detect link failures.

Referring to Fault detection, first, a Fault Primitive (FP) will be described. The fault primitive is divided into a Single-cell fault (Single-cell Faults) fault primitive and a Coupling fault (Coupling Faults) fault primitive, wherein the Single-cell fault refers to a fault which independently occurs on one storage unit and is sensitized without being influenced by other storage units, and the fault primitive is < S/F/R >; the coupling fault means that the state of one memory cell is changed due to the states or operations of other memory cells, which occur among 2 or more memory cells, and the fault primitive is < Sa, sv/F/R >, a represents the address of an attack cell, v represents the address of a victim cell, and the state of the victim cell is changed due to the states or operations of the attack cell.

In the sign of the fault primitive S, sa and Sv are referred to as sensitization operation sequences(Sensitizing operation sequence) representing the state and sequence of operations of the corresponding memory cell required for Fault sensitization, the values ranging from {0,1,0w0,1w1,0w1,1w0, r0, r1}, representing in sequence state 0, state 1, write 0 operation in state 0, write 1 operation in state 1, write 1 operation in state 0, write 0 operation in state 1, read 0 operation, read 1 operation, F being referred to as Fault behavior (Fault behavir), representing the Fault state or behavior of the faulty memory cell, the values ranging from {0,1, ，}，“"represents the rising transition of state 0 to state 1,">"represents a falling transition from state 1 to state 0; r is called a read Result (Result) and indicates a read Result when the sensitization operation sequence S/Sv of the faulty memory cell is a read operation, and R is "-" when the sensitization operation sequence S/Sv of the faulty memory cell is not a read operation, and thus the value range of R is {0,1, - }.

List one

Watch II

Watch III

The faults of the memory are classified into static faults and dynamic faults according to the operation times of the sensitization operation sequence, specifically, if the operation times are less than or equal to 1, the static faults are called, and otherwise, the dynamic faults are called. The application focuses on the detection of static faults, so that the fault primitives of various single unit faults in the static faults and the March element sequences thereof are listed through a table shown in a table I, and the fault primitives of various coupling faults in the static faults and the March element sequences thereof are listed through a table II and a table III. It should be noted that, the March element sequence corresponding to the fault primitive is used for detecting the fault described by the fault primitive, and the correspondence between the March element sequence and the fault primitive in the tables shown in the table two and the table three is set based on that the address of the attack unit in each coupling fault is higher than that of the victim unit.

Referring to the table shown in table one, a single cell failure in a static failure includes six types: status Fault (SF), transition Fault (TF), write disturb Fault (Write Disturb Fault WDF), read disturb Fault (Read Destructive Fault RDF), false read Fault (Incorrect Read Fault IRF), fraudulent read disturb Fault (Deceptive Read Destructive Fault DRDF). Each of the six single unit faults described above corresponds to 2 fault primitives and thus corresponds to a total of 12 fault primitives, and thus is also referred to as a single unit fault being subdivided into 12 types.

Referring to tables shown in tables two to three, the coupling faults in the static faults include the following seven types: status coupling faults (State Coupling Fault, CFst), coupling disturbance faults (Disturb Coupling Fault, CFds), coupling conversion faults (Transition Coupling Fault, CFtr), coupling read fault faults (Read Destructive Coupling Fault, CFrd), coupling error read faults (Incorrect Read Coupling Fault, CFir), coupling write fault faults (Write Destructive Coupling Fault, CFwd), coupling spoofing read fault faults (Deceptive Read Destructive Coupling Fault, CFdrd), wherein the coupling disturbance faults are subdivided into coupling disturbance read faults (CFdsrx), coupling disturbance same status write faults (CFdsxwx) and coupling disturbance opposite status write faults (CFdsxw | x), and can be considered as coupling faults comprising nine subdivisions. Each of the nine sub-divided coupling faults corresponds to 4 fault primitives and thus 36 fault primitives in total. If the order of the attacking unit and the victim unit in the coupling fault is considered, that is, the order of the address of the attacking unit being higher than the address of the victim unit and the address of the attacking unit being lower than the address of the victim unit is considered, the coupling fault can be considered to be further subdivided into 72 kinds in total.

In the tables shown in tables one to three, one fault primitive corresponds to one or more March element sequences. The March element sequence generally includes a plurality of March elements, one March element describing one step performed on all storage units in the storage space to be tested in the March class test method, and one March element sequence representing a test method for a fault described in a corresponding fault primitive. The basic idea of the March test method is that after performing read-write operation on one storage unit, sequentially proceeding to the next storage unit and performing read-write operation on the proceeding storage unit, so that one March element describes the proceeding sequence and the read-write operation on the proceeding storage unit, and thus the March element contains symbols "∈", and the like "One of the symbols of the read and write operations followed by the symbol "∈" wherein the symbol "∈" indicates proceeding in ascending order of address, "∈" indicates proceeding in descending order of address, "- ∈">"means proceeding in either an ascending address order or a descending address order.

The March element sequence corresponding to the first fault primitive of the conversion fault in the table one is exemplified, wherein the March element(w 1) means performing a write 1 operation in an ascending address order or a descending address order, that is, performing a write 1 operation on each memory cell in sequence starting from the highest address or the lowest address of the memory space to be tested; march element- >(w 0, r 0) means that the write 0 operation and the read 0 operation are performed in ascending order of addresses or descending order of addresses, that is, the write 0 operation and the read 0 operation are performed on each memory cell in sequence from the highest address or the lowest address of the memory space to be tested, and it should be noted here that the write 0 operation and the read 0 operation are performed on the memory cell currently being traveled to are performed before the next memory cell is traveled to after the end. The first fault primitive of the transition fault in the table one indicates that the victim unit has a fault in writing 0 in the 1 state, the fault behavior is a rising transition from the correct state 0 to the error state 1, and thus the victim unit is written with 1 first and then written with 0 and then read with 0 according to the corresponding March element sequence, wherein the write 0 operation is performed in the 1 state of the victim unit, and thus the victim unit is still in the 1 state, so that the data 1 is read in the read 0 operation, that is, the data 1 read in the read 0 operation is inconsistent with the expected data 0, and the fault indicated by the first fault primitive of the transition fault in the table one is determined. It can also be seen that the March element sequence determines that the storage unit has a fault corresponding to the March element sequence through the inconsistency of the data read in the read operation and the expected data.

The March element sequences shown in tables two to three are the case where the attack unit address is higher than the victim unit address in the corresponding coupling failure.

A link failure, i.e. the behavior that one failure may affect other failures, is shown in fig. 1 as a typical link failure. Referring to fig. 1, fig. 1 (a) and fig. 1 (b) represent two independent coupling faults, wherein fig. 1 (a) represents a fault corresponding to a first fault primitive in the coupling conversion fault shown in table three, and a corresponding March element sequence in table three can be usedw0 ≡ (w 1, r 1) to detect the fault, the attack unit is a1, the victim unit is v1, and this coupling relationship is expressed as: a1→v1, (b) in FIG. 1 shows a fault corresponding to the first fault primitive in the coupling disturbance opposite state write fault shown in Table three, the corresponding March element sequence +.>w0 ∈ (r 0, r 1) to detect the fault, the attack unit is a2, the victim unit is v2, and this coupling relationship is expressed as: a2→v2. If the victim cell v1 in fig. 1 (a) and the victim cell v2 in fig. 1 (b) are the same victim cell, as shown in fig. 1 (c), the failure shown in fig. 1 (a) and the failure shown in fig. 1 (b) are linked, and a link failure is formed.

It should be noted that the coupling transition fault refers to a fault occurring in the state transition of the victim unit when the aggressor unit is in a certain definite state, and is the first fault primitive in the coupling transition fault shown in the table three<0;0w1//->Indicating that the victim unit fails in state 0, i.e. the failure behavior of the victim unit is represented by a falling transition from correct state 1 to error state 0, when the aggressor unit is in state 0, such that the victim unit is still in state 0 due to failure after write 1 operation, thus the failure primitive<0;0w1//->Can also be expressed as<0;0w1/0/->. Similarly, a coupling disturbance opposite state write failure refers to the change of the state of the victim cell caused by the opposite state write operation of the aggressor cell, and the coupling disturbance opposite state write failure is shown in the third table as the first failure primitive<0w1;0//->Indicating that writing 1 in state 0 by an attacking cell causes state 0 of the victim cell to change, i.e. the failure behavior of the victim cell is manifested as a rising transition from correct state 0 to error state 1, such that the victim cell is in state 1 due to a failure, and thus the failure primitive described above<0w1;0//->Can also be expressed as<0w1;0/1/->。

Shown in FIG. 1 (c)If March element sequence is to be used in the link failure of (a)The detection of the coupling transition fault applied to the victim cell by w0+.1 (w 1, r 1) is performed in the process of writing 1 read 1 in the ascending address order after the write 0 operation, the victim cell is in the error state 0 when the attack cell a1 is in the state 0 and the fault exists when writing 1 in the state 0, but since the attack cell a1 and the attack cell a2 corresponding to the victim cell are both in the state 0 at this time, it is not possible to determine which of the two attack cells the coupling transition fault attack cell is by reading the data "0" in the read 1 operation. Also in this link failure, if the March element sequence is +. >The detection of the reverse state write fault of the coupling interference applied to the victim cell by w0 ∈ (r 0, w 1) is that the attack cell a2 changes the state 0 of the victim cell to be in the error state 1 when the write 1 is read in the descending order of addresses after the write 0 operation, but since the subsequent victim cell also performs the write 1 operation in the state 0 when the read 0 operation is performed by the attack cell a1, the data "1" is read out in the read 0 operation of the victim cell and the attack cell of the reverse state write fault of the coupling interference can be determined as one of the two attack cells. That is, the two faulty links cause the March element sequence judgment coupling unit to collide, and the fault is masked.

In order to test static link faults in industry, six March elements M0, M1, M2, M3, M4 and M5 are obtained by reasonably setting test steps, and the six March elements form a March LR March test method, and the method is specifically shown in the following table IV:

table four

The test procedure described for each of the six March elements is described above with respect to the March elements and will not be described in detail here.

A write disturb failure refers to a write operation that does not change state when a write operation is performed on a victim cell, causing the victim cell to transition state. For example, the victim cell is preceded by a state 0, then a 0 is written but the state transitions to a 1. The coupled write failure refers to triggering the victim unit to generate write disturbance failure when the attack unit is in a certain determined state.

A spoofed read failure refers to a read operation of a victim cell causing a change in the state of the victim cell, but the read operation reads the state prior to the change. For example, the victim cell is previously state 0, and is read to jump its state to 1, but the read data is still 0. The coupling spoofing read failure fault refers to triggering the victim unit to generate the spoofing read failure when the aggressor unit is in a certain state.

TABLE five

In view of the above, the present application compares the fault primitives corresponding to the write disturb fault, the spoofed read destroy fault, the coupled write destroy fault, and the coupled spoofed read destroy fault, respectively, to find: the fault primitive of the write disturbance fault is contained in the coupling write damage fault, and the fault primitive of the deceptive read damage fault is contained in the fault primitive of the coupling deceptive read damage fault, and the specific table is shown in a fifth table. Thus, as long as the new test method is able to detect both coupled write disturb faults and coupled fraudulent read disturb faults, it is also ensured that write disturb faults and fraudulent read disturb faults can be detected. Based on the method, the test method for detecting the memory faults provided by the embodiment of the application is obtained by improving the March LR test method based on March elements according to the fault primitive of the coupling deceptive read destructive faults, so that the improvement of the fault detection coverage rate is realized.

Fig. 2 is a flowchart of a test method for detecting a memory failure according to an embodiment of the present application. Referring to fig. 2, the test method includes:

step S110, performing multiple read-write operations on a storage space to be tested of the memory;

and step S120, comparing the data read in the multiple read-write operations with expected data to determine whether the addresses in the storage space to be tested have faults.

The multiple read/write operations in step S110 include:

a first write operation S111 of performing write 0 operation in descending address order or ascending address order;

a first read-write operation S112, wherein the read 0 operation and the write 1 operation are performed according to the descending order of addresses;

a second read-write operation S113, performing a plurality of read 1 operations, write 0 operations, read 0 operations, write 1 operations in ascending order of addresses;

a third read-write operation S114, performing a read 1 operation, a write 0 operation, and at least one read 0 operation in ascending order of addresses;

a fourth read-write operation S115, performing a plurality of read 0 operations, write 1 operations, a plurality of read 1 operations, and write 0 operations in ascending order of addresses;

the first read operation S116 performs a read 0 operation in ascending order of addresses.

In the above-described multiple read/write operations, the read 0 operation is an operation for reading the desired data 0, and if the read data is 1, the read data and the desired data 0 are inconsistent; the read 1 operation is an operation for desirably reading data 1, and if the read data is 0, the read data and the desired data 1 do not coincide.

Specifically, in order to control the time complexity, the above test method is performed once if a certain read operation or write operation is not emphasized more than once, and is performed twice if a certain read operation or write operation is emphasized more than once, in which case the six steps included in the above test method can be described by six new March elements M0', M1', M2', M3', M4', and M5', as shown in the following table six:

TABLE six

Compared with six March elements included in the March LR in the existing test method, the six new March elements in the test method provided by the application only have read operations added to each of the March elements M2', M3' and M4', and symbols of the read operations added to the three new March elements are indicated by bold. In other words, the March element M2' is added with a read 1 operation before the write 0 operation of the March element M2, the March element M3' is added with a read 0 operation after the write 0 operation of the March element M3, and the March element M4' is added with a read 0 operation before the write 1 operation of the March element M4 and added with a read 1 operation between the write 1 operation and the read 0 operation of the March element M4. Because the six new March elements are sequentially executed according to the sequences of M0', M1', M2', M3', M4', M5' in the execution process of the test method, the read operations added by the March elements M2', M3' and M4' are adjacent to an original same read operation, so that the improvement does not affect the detection of static link faults, but increases the detection functions of deceptive read damage faults and coupling deceptive read damage faults.

For the same reason, any of the embodiments of the improved method of FIG. 2 can cover the detection of static link failures as well as fraudulent read corruption failures and coupling fraudulent read corruption failures, regardless of control time complexity.

Further, the test method further comprises: under the condition that the data read by an address in the storage space to be tested is inconsistent with the expected data, outputting the address and outputting the identification of the read operation for reading the data, so that a user only needs to analyze the output data, wherein the output address is convenient for the user to directly determine which storage unit in the storage space to be tested has faults, and the output identification is convenient for the user to analyze the types of the faults. The identification herein specifically indicates which one of the above six steps is operated or which sub-step is.

Watch seven

The table shown in the seventh table describes the steps corresponding to the sensitization operation and the test operation respectively in the coupling deceptive read damage fault detection by the test method in the related language of March elements, and the steps described in the language are sub-steps of the March elements before the colon, which are sequenced into numbers after the colon. For example, M4':2 describes a second sub-step of March element M4', namely a second read 0 operation in a fifth step S5.

It should be noted that the sensitization operation causes the failure of the victim cell to occur, the test operation causes the failure of the victim cell to manifest, and the test operation is a read operation. FIG. 3 shows the sensitization and testing states of a memory cell at address v during execution of a March element sequence of a fault, which is a fault primitive in a coupled fraudulent read failure<0;r0//0>The described fault, i.e. the victim unit read 0 operation in case of an attack unit being state 0 causes the rising transition of itself from the correct state 0 to the error state 1, but the data read at this time is not affected and still is the correct data 0, the March element sequence is->w0(r 0, r 0). Referring to FIG. 3, the memory space to be tested is memory locations at addresses 0 through n, where address a is higher than address v, and the memory location at the current address v to be tested has a fault primitive as to whether the memory location at address a will have a fault<0;r0//0>The described fault, therefore, the test procedure is to perform the write 0 operation in the ascending address order or descending address order, after which the state of each memory cell in the memory space to be tested is as the first column of data in the figure, and then perform the read 0 operation in the ascending address order or descending address order twice, wherein the first read 0 operation is the sensitization operation, after which the data read out from each memory cell in the memory space to be tested is as the second column of data in the figure, and for the memory cell at the address v, the read 0 is in the sensitization state (0, r 0) when in the state 0; the second read 0 operation is a test operation, and after the test operation is performed, the data read out from each memory cell in the memory space to be tested is shown as the third column of data, and for the memory cell at the address v, the memory cell is in the test state (0, r 0) because it is in the state 0. Where the memory cell at address v is in the test state (0, r 0) because it does not have a fail primitive due to the memory cell at address a <0;r0//0>The fault described. If the storage unit at the address v has a fault primitive due to the storage unit at the address a<0;r0//0>The described failure, the memory cell at address v can be read out for correct data 0 after the first read 0 operation but a rising transition of correct state 0 to error state 1 will occur, so that the memory cell at address v can be read out for error data 1 after the second read 0 operation, i.e. the failure is made visible, in which case it is in test state (1, r 0) for the memory cell at address v which is read 0 in state 1.

Referring to Table seven, for failure primitives<0;r0//0>The described coupling deceptive read damage fault, the sensitization operation is M4':1, namely the first read 0 operation in the fourth read-write operation S115; the test operation is M4' to 2, namely the second time of reading 0 operation in the fourth reading and writing operation S115. For fault primitives<1;r0//0>The described coupling deceptive read damage fault, the sensitization operation is M3':3, namely the read 0 operation in the third read-write operation S114; the test operation is M4' 1, namely the first read 0 operation in the fourth read/write operation S115. Fault primitives<0;r1//1>The described coupling deceptive read damage fault, the sensitization operation is M4':4, namely the first read 1 operation in the fourth read/write operation S115; the test operation is M4':5, the second read 1 operation in the fourth read/write operation S115. Fault primitives <1;r1//1>The described coupling deceptive read damage fault, the sensitization operation is M2':1, namely the read 1 operation in the second read-write operation S113; the test operation is M2':2, namely the second read 1 operation in the second read/write operation S113.

Since the fault primitive of the fraudulent read damage fault is contained in the fault primitive of the coupling fraudulent read damage fault, in the case that an address in the storage space to be tested has the fraudulent read damage fault or the coupling fraudulent read damage fault, the output identifier includes any one of the following: the identification of the first read 0 operation in the fourth read/write operation S115, the identification of the second read 1 operation in the fourth read/write operation S115, and the identification of the second read 1 operation in the second read/write operation S113.

Further, if an address in the memory space to be tested has a coupling spoofing read failure fault, the address of the attack unit in the coupling spoofing read failure fault obtained based on the output identification analysis is higher than the address of the victim unit.

The following fault primitives listed in the table shown in table seven<0;r0//0>The described coupling deceptive read failure is taken as an illustration of a sensitization operation and a test operation, and specifically corresponds to an attack ticket The meta address is higher than the victim cell address. The test process adopts the implementation mode with the minimum time complexity in the test method shown in fig. 2, and thus the test process is as follows: the first writing operation S111 is executed, and each memory cell in the memory space to be tested writes 0; the first read-write operation S112 is performed, the attack unit performs a read 0 operation and a write 1 operation so as to be in a state 1, and then the victim unit performs a read 0 operation and a write 1 operation; the second read-write operation S113 is performed, the victim unit performs the read-1 operation, the write-0 operation, the read-0 operation, and the write-1 operation twice, and then the attack unit performs the read-1 operation, the write-0 operation, the read-0 operation, and the write-1 operation twice so as to be in the state 1; the third read-write operation S114 is performed, the victim unit performs a read 1 operation, a write 0 operation, and a read 0 operation, and then the attack unit performs a read 1 operation, a write 0 operation, and a read 0 operation to be in a state 0; the fourth read/write operation S115 is performed, the victim unit first performs a read 0 operation (i.e., M4': 1), at which time the failure occurs because the aggressor unit is in state 0, resulting in a rising transition from the correct state 0 to the error state 1, and then the victim unit performs a read 0 operation again (i.e., M4': 2) to read out the data 1, revealing the failure. It can be seen that: operation M4':1 is a sensitization operation, and operation M4':2 is a test operation.

The above analysis process further illustrates that the test method provided by the embodiment of the application can detect the fault primitive<0;r0//0>The described coupling fraudulently reads the destructive fault. For other types of coupled fraudulent read corruption faults and fraudulent read corruption faults, it may be determined by the above described analysis procedures that the test methods provided by embodiments of the present application can be tested, and will not be described in detail herein.

Further, the first write operation S111 performs the write 0 operation in descending order of address and the write 0 operation is repeated a plurality of times; the write 1 operation of the first read/write operation S112 is repeated a plurality of times; the write 0 operation of the third read-write operation S114 is repeated a plurality of times; the write 1 operation of the fourth read/write operation S115 is repeated a plurality of times, thereby obtaining a further improved test method, as shown in fig. 4. Since the improvement is the repeated execution of the existing operation, the original static link fault detection function and the detection function of the deceptive read damage fault and the coupling deceptive read damage fault are not affected under the condition that the detection functions of the write disturbance fault and the coupling write damage fault are newly added. Based on this, in the case that there is a spoofed read failure or a coupled spoofed read failure at an address in the memory space to be tested, the output identifier still includes any one of the following: the identification of the first read 0 operation in the fourth read/write operation S115', the identification of the second read 1 operation in the fourth read/write operation S115', and the identification of the second read 1 operation in the second read/write operation S113 '.

Specifically, in order to control the time complexity, the test method shown in fig. 4 is performed once if a certain read operation or write operation is not emphasized more than once, and is performed twice if a certain read operation or write operation is emphasized more than once, and six steps included in the test method further improved in this case can be described by six March elements M0', M1 ", M2", M3 ", M4", and M5 "as shown in the following table eight:

table eight

Table nine

The table shown in table nine describes the steps corresponding to each of the sensitization operation and the test operation in the coupled write damage fault detection by the test method further improved as described above in the relevant language of March elements. Referring to Table nine, for failure primitives<0;0w0//->The described coupled write failure, sensitization operation is M0' ':2, the second write 0 operation in the first write operation S111 '; the test operation is M1' ' to 1, i.e., a read 0 operation in the first read/write operation S112 '. For fault primitives<1;0w0//->The described coupled write damage fault, sensitization operation is M3' ':3, namely the second write 0 operation in the third read-write operation S114 '; the test operation is M3' ' to 4, namely, the read 0 operation in the third read/write operation S114 '. Fault primitives<1;1w1//->The described coupled write damage fault, sensitization operation is M1' ' to 3, namely the second write 1 operation in the first read-write operation S112 '; the test operation is M2' ' to 1, namely the first read 1 operation in the second read/write operation S113 '. Fault primitives <0;1w1//->The described coupled write failure, sensitization operation is M4' ':4, the second write 1 operation in the fourth read/write operation S115 '; the test operation is M4' ' to 5, the first read 1 operation in the fourth read/write operation S115 '.

Since the fault primitive of the write disturb fault is included in the fault primitive of the coupling write disturb fault, in the case that an address in the storage space to be tested has the write disturb fault or the coupling write disturb fault, the output identifier includes any one of the following: the identification of the read 0 operation in the first read/write operation S112', the identification of the read 0 operation in the third read/write operation S114', the identification of the first read 1 operation in the second read/write operation S113', and the identification of the first read 1 operation in the fourth read/write operation S115'.

Further, if an address in the storage space to be tested has a coupling write failure or a coupling spoofing read failure, the address of the attack unit in the coupling write failure and the coupling spoofing read failure obtained based on the identification analysis of the output is higher than the address of the victim unit.

The determination of the various coupled write damage fault sensitization operations and test operations shown in Table nine above may be described with reference to Table seven, and the determination of the write disturbance fault, the fraudulent read damage fault, and the coupled fraudulent read damage fault respective sensitization operations and test operations may also be described with reference to Table seven.

Fig. 5 (a) shows the execution timing chart of the first write operation S111 'in the further improved test method, fig. 5 (b) shows the execution timing chart of the first read/write operation S112' in the further improved test method, fig. 5 (c) shows the execution timing chart of the second write operation S113 'in the further improved test method, fig. 5 (d) shows the execution timing chart of the third write operation S114' in the further improved test method, fig. 5 (e) shows the execution timing chart of the fourth write operation S115 'in the further improved test method, and fig. 5 (f) shows the execution timing chart of the first read operation S116' in the further improved test method. The read-write operations in the test method after further improvement shown in each of the six execution timing diagrams are all started from the dashed line, and each corresponds to the implementation mode with the minimum time complexity in the test method shown in fig. 4, wherein mbist_control_1 is a test start signal, and the test stage is entered when the test is at a high level; the mbist_clk is a clock signal, and performs a read operation or a write operation in one clock cycle; mbist_nrst is a reset signal; test_RWB_0 is a read-write control signal, and is read when writing high level at low level; tstate is a status signal, which of six steps in the test is controlled to be executed, wherein the first step S1 'after the improvement is controlled to be executed when the value is' 01101 ', the second step S2' after the improvement is controlled to be executed when the value is '01111', the third step S3 'after the improvement is controlled to be executed when the value is' 01111 ', the fourth step S4' after the improvement is controlled to be executed when the value is '01110', the fifth step S5 'after the improvement is controlled to be executed when the value is' 01011 ', and the sixth step S6' after the improvement is controlled to be executed when the value is '01011'; test_A_0 is an address signal and indicates a memory cell of the current read-write operation; test_DI_0 is an input signal, i.e., data written in a write operation, which is not considered in a read operation; test_DO_0 is an output signal, i.e., data read by a read operation, indicating the read data at the end of the read operation, and the signal is not considered during a write operation; mbist_fail_o_0 is a fault indication signal, and a high level indicates that a fault is detected; mbist_done_0 is the end of test signal, and a high level indicates the end of test. It should be noted that, in each of the above-described execution timing diagrams, the data consistent with the expected data is read by properly setting the initialization state to have no read operation under the fault condition, and thus the fault indication signal mbist_fail_o_0 is always low. In these execution timing charts, "FFFF" indicates that the data written or read is 1, and "0000" indicates that the data written or read is 0; the highest address of the memory space to be tested is 1FFF, the lowest address is 0000, and each execution time sequence chart only shows the read-write operation of part of memory units at the beginning of the corresponding step.

FIG. 6 illustrates a fault primitive that exists for memory according to one test method illustrated in FIG. 4<1;0w0//->The timing diagram for fault detection is described, corresponding to the embodiment with the least time complexity in the test method shown in fig. 4. As shown in fig. 6, in the Test stage with the state signal tstate being 01110, the output signal test_do_0 corresponding to the last read operation in the Test process with the address signal test_a_0 being 0001 is "FFFF" (shown by dotted line frame), and the fault indication signal mbist_fail_o_0 is at high level, i.e. the last read operation of the third read/write operation S114' in the Test method after further improvement reads 0 error in the memory cell at the address 0001, thereby detecting the fault, i.e. M3 "to 4 is the fault primitive as shown in table nine<1;0w0//->The described coupled write destroys the failed test step and in this case the address of the aggressor cell is higher than the address of the victim cell.

FIG. 7 illustrates a fault primitive that exists for memory according to one test method illustrated in FIG. 4<0;1w1//->The timing diagram at the time of fault detection is described and corresponds to the embodiment of the test method of fig. 4 where the time complexity is minimal. As shown in fig. 7, in the Test phase of the state signal tstate being 01010, the output signal test_do_0 corresponding to the third read operation is "during the Test of the address signal test_a_0 being 0000" 0000 (dotted line frame in the figure), at which time the fault indication signal mbist_fail_o_0 is high, i.e. the third read operation of the fourth read/write operation S115' reads 1 error at the memory cell at address 0000, thereby detecting a fault, i.e. m4″ to 5 is a fault primitive as shown in table nine<0;1w1//->The described coupled write destroys the failed test step and in this case the address of the aggressor cell is higher than the address of the victim cell.

The test method shown in fig. 4 can detect all Static link faults and various Static unlink faults commonly encountered in reality, and can improve the fault coverage rate of Static Random-Access Memory (SRAM) in the process of 40nm and below by using the test method. Since the time complexity of each read operation or write operation in the March class test method is regarded as 1, the test method shown in fig. 4 has a minimum time complexity of only 22N, and the time complexity is not high.

Corresponding to the test method for detecting a memory failure provided in the above embodiment, another embodiment of the present application further provides a test circuit implementing any one of the test methods described in the above embodiments, which has a higher failure detection coverage rate and is not high in time complexity. Fig. 8 is a circuit diagram of a test circuit for detecting a memory failure according to an embodiment of the present application. Referring to fig. 8, the test circuit 10 includes: an address generating unit 11 for generating an address of a memory cell to be tested, such as the address signal test_a_0 in the Test example described above; a data generating unit 12 for generating data to be written to the memory cell to be tested indicated by the address, such as the input signal test_di_0 in the Test example described above; a control signal generating unit 13, configured to generate a control signal test_cont to control performing a read operation of the multiple read-write operations in step S110 on the memory unit to be tested indicated by the address, or performing a write operation of the data of the multiple read-write operations in step S110 on the memory unit to be tested indicated by the address; and a comparing unit 14, configured to compare the data read out in the multiple read-write operations in step S110 with expected data, so as to determine whether there is a failure in the address in the storage space to be tested.

Specifically, the control signal test_cont may include, as shown in the above Test example: test start signal mbist_control_1, clock signal mbist_clk, reset signal mbist_nrst, read/write control signal test_rwb_0, status signal tstate, test end signal mbist_done_0. The address generating unit 11 and the data generating unit 12 are controlled by a control signal test_cont, for example, generating respective signals based on a clock signal mbist_clk at a Test stage indicated by a Test start signal mbist_control_1 and a Test end signal mbist_done_0. Further, the comparing unit 14 may compare the output signal test_do_0 shown in the above Test example with the signal representing the desired data to obtain a comparison result, where the comparison result is that there is a failure of an address in the memory space to be tested in the case where the output signal test_do_0 and the signal representing the desired data are inconsistent.

Further, as shown in fig. 9, the test circuit 10 further includes: an output unit 15 for outputting, as output data test_out, an address of the corresponding read data and an identification of a read operation of the read data in a case where the comparison result obtained by the comparison unit 14 is inconsistent. Specifically, the output unit 15 may output and output the address signal test_a_0, the clock signal mbist_clk, the read/write control signal test_rwb_0, the status signal tstate to indicate the failed address and the identification of the read operation of reading out the data inconsistent with the desired data, as shown in the above Test example.

These embodiments are not all described in detail and are not limiting of the application to only the specific embodiments described, as described above in accordance with the embodiments of the application. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. This application is to be limited only by the claims and the full scope and equivalents thereof.

Claims

1. A test method for detecting a memory failure, comprising:

wherein, the multiple read-write operations include:

2. The test method of claim 1, further comprising: and outputting the address and outputting the identification of the read operation for reading the data under the condition that the data read by the address in the storage space to be tested is inconsistent with the expected data.

3. The test method according to claim 2, wherein in case of a fraudulent read corruption failure or a coupling fraudulent read corruption failure of an address in the memory space to be tested, the identification comprises any one of the following: the identification of the first reading 0 operation in the fourth reading and writing operation, the identification of the second reading 1 operation in the fourth reading and writing operation and the identification of the second reading 1 operation in the second reading and writing operation.

4. The test method of claim 3, wherein the coupling spoofing read destroys an address of an attacking cell higher than an address of a victim cell in the fault.

5. The test method according to claim 2, wherein,

the first write operation performs write 0 operation in descending order of addresses and the write 0 operation is repeated for a plurality of times;

6. The test method according to claim 5, wherein, in the case that an address in the memory space to be tested has a write disturb failure or a coupled write disturb failure, the identification includes any one of the following: the identification of the read 0 operation in the first read-write operation, the identification of the read 0 operation in the third read-write operation, the identification of the first read 1 operation in the second read-write operation, and the identification of the first read 1 operation in the fourth read-write operation.

7. The test method of claim 6, wherein the coupled write destroy fault attack cell has an address higher than an address of a victim cell.

8. The test method according to claim 1, wherein,

performing write 0 operation in the first write operation once;

the read 0 operation in the first read operation is performed once.

9. A test circuit for implementing the test method of any one of claims 1-8, comprising:

10. The test circuit of claim 9, further comprising: