CN114974389A

CN114974389A - Storage device and test method and test system thereof

Info

Publication number: CN114974389A
Application number: CN202210581391.5A
Authority: CN
Inventors: 陈剑锋
Original assignee: Hefei Kangxinwei Storage Technology Co Ltd
Current assignee: Hefei Kangxinwei Storage Technology Co Ltd
Priority date: 2022-05-26
Filing date: 2022-05-26
Publication date: 2022-08-30

Abstract

The invention discloses a test method of storage equipment, which at least comprises the following steps: providing a storage device, and establishing a data area, a system block area and a bad block table mapping area in the storage device according to the type of the storage information; performing a first read-write test on the data area, and establishing a first bad block area and a working block area in the data area according to the result of the first read-write test; adjusting the time sequence information of the storage equipment, acquiring read-write error information of a working block area, and repeatedly tuning the read-write parameter information of the storage equipment according to the read-write error information; performing a second read-write test on the working block area and the system block area according to the read-write parameter information, and marking a second bad block area in the working block area and the system block area according to the result of the second read-write test; and obtaining bad block information of the first bad block area and the second bad block area, and recording the bad block information in a bad block table mapping area. The method and the device can quickly and stably screen out the bad blocks in the storage equipment.

Description

Storage device and test method and test system thereof

Technical Field

The invention belongs to the field of storage device testing, and particularly relates to a storage device, a testing method and a testing system thereof.

Background

Flash Memory (Flash Memory) is a long-lived, non-volatile Memory. Flash memory can be deleted and adapted in units of memory called blocks. The writing operation of the flash memory must be performed in a blank area, and if the target area has data, the data must be written after being erased, so the erasing operation is the basic operation of the flash memory. In the manufacturing process of flash memory, a bad block problem occurs due to process limitations and flash memory performance problems.

When a flash memory has a bad block, the storage device cannot accurately test the bad block, and if the bad block is used during data storage, errors occur in reading and writing and erasing of data. The existence of bad blocks can seriously affect the performance of the hard disk and even cause the rejection of the hard disk and the data loss.

Disclosure of Invention

The invention aims to provide a storage device, a test method and a test system thereof, which can quickly and stably screen out bad blocks in the storage device, thereby improving the stability of the storage device.

In order to solve the technical problems, the invention is realized by the following technical scheme:

the invention provides a test method of storage equipment, which at least comprises the following steps:

providing a storage device, and establishing a data area, a system block area and a bad block table mapping area in the storage device according to the type of storage information;

performing a first read-write test on the data area, and establishing a first bad block area and a working block area in the data area according to the result of the first read-write test;

adjusting the time sequence information of the storage equipment, acquiring the read-write error information of the working block area, and repeatedly tuning the read-write parameter information of the storage equipment according to the read-write error information;

performing a second read-write test on the working block area and the system block area according to the read-write parameter information, and marking a second bad block area in the working block area and the system block area according to the result of the second read-write test; and

and obtaining bad block information of the first bad block area and the second bad block area, and recording the bad block information in the bad block table mapping area.

In an embodiment of the present invention, the step of tuning the read-write parameters of the storage device includes:

writing data into the work block area at a single data rate, and reading data from the work block area at a double data rate; and

and correcting the time sequence information of the reading stage according to the error correction code generated by the read-write data to obtain the optimal reading time sequence information.

adjusting the time sequence information of the storage equipment to be optimal reading time sequence information, and writing data into the working block area at double data rate;

and reading data from the working block area, and correcting the time sequence information of the writing stage according to an error correction code generated by the read-write data to obtain the optimal writing time sequence information.

In an embodiment of the present invention, after repeatedly tuning the read-write parameter information of the storage device, a result page of a storage block in the storage device is searched, and a bad block mapping table is established in the bad block mapping table area, where the bad block mapping table includes a bad block address and bad block information of the first bad block area.

In an embodiment of the present invention, the step of the first read-write test includes:

providing a plurality of preset data, and writing the preset data into the working block area according to the sequence of the preset data from large to small until the working block area is fully written; and

and reading the preset data and recording error correction codes generated in the process of reading and writing the data.

In an embodiment of the present invention, after the bad block mapping table is established, a pretest is performed on the storage device before the second read/write test.

In an embodiment of the present invention, the step of the second read/write test includes:

erasing the storage information of the storage block to be tested;

writing data into all storage pages of the storage block to be tested; and

and reading all storage pages of the storage block to be tested.

In an embodiment of the present invention, the step of marking the second bad block area includes:

editing a logic address of a system block area, and establishing a first test part and a second test part in the system block area;

performing a second read/write test on the first test portion and the second test portion; and

and marking and replacing the bad blocks in the system block area according to the error correction codes in the second read-write test process.

In an embodiment of the present invention, the step of marking the second bad block area includes: and in the process of the second read-write test, the storage information of the first test part and the second test part is backed up and stored mutually.

In an embodiment of the present invention, the step of establishing the first test section and the second test section includes:

and editing the logic address of the system block area to enable the first test part and the second test part to comprise the same number of parameter blocks, code blocks and power-on reset data storage blocks.

The invention provides a test system of a storage device, which comprises:

the partition module is used for establishing a data area, a system block area and a bad block table mapping area in the storage equipment according to the type of the storage information;

the first read-write test module is used for carrying out a first read-write test on the data area and establishing a first bad block area and a working block area in the data area according to the result of the first read-write test;

the tuning module is used for adjusting the time sequence information of the storage equipment, acquiring the read-write error information of the working block area, and repeatedly tuning the read-write parameter information of the storage equipment according to the read-write error information;

a second read-write test module, configured to perform a second read-write test on the working block area and the system block area according to the read-write parameter information, and mark a second bad block area in the working block area and the system block area according to a result of the second read-write test

And the filing and recording module is used for acquiring the bad block information of the first bad block area and the second bad block area and recording the bad block information in the bad block table mapping area.

The invention provides a storage device having a computer program stored thereon, which, when executed by a processor, implements a method of testing a storage device as claimed in claim 1.

As described above, the present invention provides a storage device, a test method thereof, and a test system, which can quickly and stably screen out a bad block in the storage device in an aging test environment, and the test method can eliminate parameter interference and consider the influence of environmental factors on the storage device as much as possible, thereby ensuring high accuracy of bad block testing. The test method and the test system provided by the invention have the advantages that the test architecture is accurate, the code redundancy in the test process is favorably reduced, and the test is favorably carried out for multiple times.

Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a flash memory chip.

Fig. 2 is a schematic diagram of a dividing structure of a flash memory chip obtained by the testing method according to the present invention.

FIG. 3 is a flow chart of a testing method of the memory device according to the present invention.

Fig. 4 is a flowchart of the test of step S20.

Fig. 5 is a flowchart of the test of step S30.

Fig. 6 is a flowchart of the test of step S34.

Fig. 7 is a flowchart of the test of step S35.

Fig. 8 is a flowchart of the test of step S40.

Fig. 9 is a flowchart of the test of step S42.

Fig. 10 is a test structure diagram of a system block area.

Fig. 11 is a flowchart of the test of step S50.

Fig. 12 is a test structure diagram of a bad block area.

Fig. 13 is a schematic structural diagram of a test system.

Fig. 14 is a schematic block diagram of a structure of a memory device.

Fig. 15 is a schematic block diagram of a structure of a computer-readable storage medium.

Description of reference numerals: 1. a flash memory chip; 10. flashing particles; 20. a storage module; 30. a storage block; 40. a data area 401, a work block area; 402. a bad block area; 4021. a bad block area of an original factory; 4022. a first bad block area; 4023. a second bad block area; 4024. a first bad block; 4025. a second bad block; 50. a system block area; 51. a first test section; 52. a second testing section; 501. a parameter block; 5011. a first parameter block; 5012. a second parameter block; 502. a code block; 5021. a first code block; 5022 a second code block; 503. a power-on reset data storage block; 5031. a first power-on reset data storage block; 5032. a second power-on reset data storage block; 60. a bad block table mapping area 70, a test system 701 and a partition module; 702. a first read-write test module; 703. a tuning module; 704. a second read-write test module; 705. a filing recording module; 80. a processor; 90. a memory; 100. computer instructions; 1001. a computer readable storage medium.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The storage device is, for example, a solid state disk, and whether the solid state disk is durable or not, whether the performance is seriously reduced during use, depends on the quality of the flash memory and the flash memory testing capability of a solid state disk manufacturer. Under different application requirements, the quality requirements of the storage device are different, for example, when the flash memory is applied to the fields of military, vehicle-mounted, aerospace and the like, the bad block rate is guaranteed not to exceed 2%, for example. When the flash memory is used, the solid state disk master control still needs to execute strategies such as bad block management and bad block replacement on the flash memory so as to guarantee the service life and the performance of the solid state disk. In application fields with strict requirements on bad blocks, such as military, vehicle-mounted and aerospace fields, once a bad block is found, the solid state disk, such as NAND, is scrapped. Therefore, the upstream manufacturer still has limitations in testing the flash memory chip, and the final quality of the solid state disk can be guaranteed only if the solid state disk manufacturer has a strong flash memory testing capability. The flash memory chip may be a NAND flash memory, and the NAND flash memory may be a chip-class flash memory with a controller, such as an eMMC chip (Embedded Multi Media Card), an SD NAND flash memory, an SPI NAND flash memory, and the like.

The testing method of the storage device comprises the steps of S10-S50, wherein the content of the step of S10 is as follows.

And S10, providing a storage device, and establishing a data area, a system block area and a bad block table mapping area in the storage device according to the type of the storage information.

Referring to fig. 1-3, in an embodiment of the present invention, a storage device is provided, such as a flash memory chip 1, and in step S10, the flash memory chip 1 is divided into a plurality of data areas 40, a plurality of system block areas 50, and a plurality of bad block table mapping areas 60. The data area is used for storing data information, the system block area is used for storing system information, and the bad block table mapping area 60 is used for storing bad block information. In the present embodiment, the flash memory chip 1 includes a plurality of flash memory granules 10, and the flash memory granules 10 include at least one memory module 20, and the memory module 20 includes a plurality of memory blocks 30. In the flash memory chip 1, each memory block 30 has a corresponding physical address. The flash memory chip 1 may be divided into a plurality of areas according to the physical address of the memory block 30. Specifically, at least one data area 40, at least one system block area 50, and at least one bad block table mapping area 60 are correspondingly established in the storage module 20, so as to facilitate bad block screening. It should be noted that the data area 40, the system block area 50, and the bad block table mapping area 60 are divided by the kind of storage information of the storage block 30. Specifically, the physical addresses of the storage blocks 30 of the same storage information type are formed into a storage block set, and the logical addresses of the storage block set are set. In the flash memory chip 1, the data area 40, the plurality of system block areas 50, and the plurality of bad block table mapping areas 60 all have corresponding logical addresses.

Referring to fig. 2 and fig. 3, in an embodiment of the present invention, in step S10, the original bad block in the flash memory chip 1 is divided into the data area 40, and an original bad block area 4021 is established. The information of the original factory bad block is stored in the bad block mapping table, and the storage block corresponding to the bad block mapping table is divided into a bad block table mapping area 60. The original factory bad block is a bad block tested by an upstream factory when the flash memory chip 1 leaves the factory. The address information of the original factory bad block is stored in the bad block mapping table, and the original factory bad block area 4021 is established according to the address information of the original factory bad block. It should be noted that the above-mentioned areas may not be continuous in physical address.

Referring to fig. 1-3, the content of step S20 in the testing method of the memory device according to the present invention is as follows.

S20, performing a first read-write test on the data area, and establishing a first bad block area and a working block area in the data area according to the result of the first read-write test.

Referring to fig. 2 and 4, in an embodiment of the present invention, an original factory bad block area 4021 is excluded, and a first read/write test is performed on the data area 40, so as to screen out unmarked bad blocks in the data area 40. Specifically, step S20 includes steps S21 to S26.

S21, writing the predetermined data into the storage block of the data area.

S22, reading the preset data from the data area.

And S23, judging whether the read preset data and the written preset data are consistent.

And S24, if the read preset data is consistent with the written preset data, dividing the memory block to be tested into a working area.

And S25, if the read preset data and the written preset data are not consistent, dividing the tested memory block into a first bad block area.

S26, judging whether the tested memory module is written, if yes, executing step S30, otherwise, repeating step S21.

Referring to fig. 2 and 4, in an embodiment of the invention, in step S21, before the first read-write test is performed, a plurality of preset data with different sizes are set. The memory module 20 is used as a test unit to perform read/write test on the memory block 30. The memory module 30 includes a plurality of memory blocks 30, and the memory block 30 is the minimum unit of erase of the memory module 30. In this embodiment, as shown in fig. 1, the memory blocks 30 are sorted and numbered according to the physical address order of the memory blocks 30, for example, a first memory block, a second memory block, and so on, and sorted to an nth memory block, and the first memory block, the second memory block, and the nth memory block may respectively correspond to numbers 1 and 2 … … n, where n is a natural number greater than 2. In step S21, the preset data may be continuously written into the corresponding storage block 30 according to the numbering sequence of the storage blocks 30 until the storage module 20 is full, so as to improve the testing accuracy to the greatest extent and eliminate the interference due to the random reading and writing. The memory block 30 includes a plurality of memory pages, which is the minimum unit of writing of the memory module 20. The size of the preset data may occupy one or more memory pages, or one or more memory blocks. The size of the preset data is not specifically limited, and the size of the preset data may be 16KB, or may be several tens of MB to several GB, for example, 20MB or 1 GB. The maximum value of the preset data does not exceed the storage volume of the storage device, and the minimum value of the preset data is the minimum unit which can be written into the storage device, so that the preset data can be written into the storage device according to different storage devices, and the read-write information of each storage block 30 is checked. The selection sequence of the preset data is from large to small, namely the preset data with the largest data volume is written firstly, and when the residual space does not meet the requirement of writing the largest preset data, the second largest preset data is selected until the preset data can be written into the corresponding storage page. Thereby improving the write efficiency of the preset data. Through the continuous writing of the preset data, the reading and writing bad block condition of the storage block 30 can be detected, the efficiency of the storage module 20 for continuously writing data can be simultaneously checked, and the experimental result record for continuously writing the preset data can be recorded in the testing process, so that the tracing is facilitated. The writing process is suitable for writing large-volume data and is suitable for storage equipment with small storage volume. For example, 2GB of preset data is written, for example, for detecting a memory device having a memory size of 8GB to 64 GB. It should be noted that, in the above embodiments, the limitation on the size of the applicable storage device may be adjusted according to the actually tested device, and the present invention only exemplifies the size of the applicable storage device, and does not limit the specific amount of the applicable storage device.

Referring to fig. 1, fig. 2 and fig. 4, in another embodiment of the present invention, in step S21, preset data with different sizes are set, and the preset data are randomly written into the storage device. The memory module 20 can be fully written to the system for automatic error reporting, or the memory module 20 can not be fully written to realize rapid test. In this embodiment, the test accuracy is improved by writing and reading the predetermined data into and out of the memory module 20 for a plurality of turns. The total amount of the preset data written into the storage device is greater than one half of the storage amount of the storage module 20, so that the accuracy of the multi-turn test is ensured. In addition, in this embodiment, through the random writing of the preset data, the efficiency of the random writing of the data into the memory module 20 can be simultaneously checked, and the experimental result of the continuous writing of the preset data can be recorded in the test process, so as to facilitate tracing. The writing process is suitable for writing of small-volume data and is suitable for storage equipment with large storage volume. For example, 50MB or 64KB of predetermined data is written, for example, for detecting a memory device having a memory size of 32GB to 256 GB. It should be noted that, in the above embodiments, the limitation on the size of the applicable storage device may be adjusted according to the actually tested device, and the present invention only exemplifies the size of the applicable storage device, and does not limit the specific amount of the applicable storage device.

Referring to fig. 1, fig. 2 and fig. 4, in an embodiment of the present invention, in step S22, the predetermined data is read from the memory block 30 to which the predetermined data is written. In this embodiment, the preset data is written once, i.e. the preset data can be read once, so that the written and read preset data can be directly compared. In other embodiments, the prepared preset data may be written, and then step S22 is executed to read all the written preset data and compare all the written preset data with all the read preset data. In this embodiment, the order of writing and the order of reading are also compared to avoid errors in the comparison process. In step S23, the written and read data are compared to exclude bad blocks in which read/write errors occur. Wherein, whether reading and writing are in Error can be determined by the bit offset (bit) of the Error Correction Code (ECC). Specifically, whether an error occurs in the read/write process can be checked by a Low Density Parity-Check Code (LDPC Code). In step S24, the physical address of the memory block 30 in which the read/write error occurs is recorded, so that the bad block occurring in the first read/write test is marked, and the memory blocks 30 in which no bad block occurs are also listed as a set, so that the working block area 401 is formed. In step S25, the memory block 30 in which the bad block flag occurs is listed as one set, thereby being formed as the first bad block area 4022.

Referring to fig. 1, fig. 2 and fig. 4, in an embodiment of the present invention, in step S26, when the preset data is read once after the preset data is written once, it is determined whether the storage module 20 is completely written. Specifically, when the storage module 20 finishes writing the preset data once and reads the data once, the total written preset data amount and the amount difference value of the storage module 20 are determined, and whether the storage module 20 finishes writing is determined. If the predetermined data is continuously written into the memory module 20 to the fully written memory module 20, in step S26, it is determined that the total amount of the written predetermined data is equal to the volume difference of the memory module 20. If the storage module 20 has not been written, the preset data with the proper size is continuously written into the storage module 20 according to the number. If the preset data is randomly written into the memory module 20 to the preset volume, in step S26, the volume difference between the total volume of the written preset data and the preset volume is determined. If the storage module 20 has not been written, the preset data is continuously written into the storage module 20 randomly.

Referring to fig. 1-4, in an embodiment of the invention, step S20 includes a plurality of first read/write tests, wherein steps S21-S26 are performed once for one turn. In the present embodiment, step S20 is executed for 4 to 8 turns, specifically for 6 turns, for example. Through the first multi-turn read-write test, the storage block 30 with the bad block is eliminated, so that the test precision of the storage device is improved, and the interference of noise information on the test method is reduced. The noise information is, for example, the ambient temperature, and a signal of a valid signal caused by an operation error.

Referring to fig. 1-4, in an embodiment of the invention, a memory device, such as a flash memory chip 1, is placed in a burn-in tester, and a predetermined temperature of a test environment is set to, for example, 85 ℃ ± 3 ℃ before step S21 is executed. Specifically, the detection temperature of the flash memory particle temperature sensor in the flash memory chip 1 is read, and when the temperature value which accords with the preset temperature is read for multiple times, the aging test of the storage device can be started. The number of times of reading the temperature value meeting the requirement is at least 5 times, for example, so as to ensure that the test environment of the storage device is stable, and thus the accuracy of the aging test is guaranteed. Before the first read-write test, a Voltage (VCC) of a test is set to be, for example, 2 to 5V, specifically, for example, 3.3V. The initial frequency is, for example, 2 to 4MHz, specifically, for example, 3 MHz. The Command Prompt (CMD) is pulled low. After the above setting is completed, the first read-write test can be started. After the bad block is found, the bad block flag and the bad block information are stored in a result page of the bad block, where the result page may be the last memory page of the bad block. After the test is completed, the first bad block area 4022 is searched, the storage page in which the bad block information and the bad block mark are stored is found, and a bad block mapping table is constructed. Specifically, the bad block mapping area is used as a redundant area for storing bad block data and establishing a bad block mapping table corresponding to the bad block address. The bad block information includes the bad block cause, such as failure in normal reading, failure in normal writing, failure in normal erasing, overtime reading and writing, data error, and ECC code excess bit.

Referring to fig. 1-3, the content of step S30 in the testing method of the memory device according to the present invention is as follows.

And S30, adjusting the time sequence information of the storage device, acquiring the read-write error information of the working block area, and repeatedly tuning the read-write parameter information of the storage device according to the read-write error information.

Referring to fig. 1, fig. 2 and fig. 5, in an embodiment of the present invention, in the data storage process of the storage block 20, a data error occurs due to the read-write parameters, and a bad block also occurs in the first read-write test. Therefore, in step S30, the read/write parameters of the data are tuned to reduce the amount of error information during the test process and improve the test accuracy. Specifically, step S30 includes steps S31 to S36.

And S31, erasing the data stored in the work block area.

And S32, setting the initial time sequence information of the storage device, and writing data to the work block area at a single data rate.

S33, reading out data from the work block area at double data rate.

And S34, comparing the written data with the read data, and correcting the time sequence information of the reading stage to obtain the optimal reading time sequence information.

And S35, adjusting the time sequence information of the storage device to be the optimal reading time sequence information, writing data into the working block area, correcting the time sequence information in the writing stage, and obtaining the optimal writing time sequence information.

And S36, storing the optimal reading time sequence information and the optimal writing time sequence information as card-opening parameters.

Referring to fig. 1, 2, 5 and 6, in an embodiment of the invention, in step S31, the preset data written in the memory module 20 in step S20 is erased. Specifically, the preset data located in the working block area 401 and the first bad block area 4022 is erased. In step S32, initial timing information of the storage device is set, specifically, the timing information may be set to the lowest timing, and Data is written to the work block area 401 at a Single Data Rate (SDR). The written data may be preset data to reduce the redundancy of information. In step S33, Data is read out from the work block area 401 at Double Data Rate (DDR). And in step S34, the error correction code is used to confirm the data error condition, so as to adjust and obtain the optimal timing information. Specifically, step S34 includes steps S341 to S345.

S341 determines whether or not the data read from the work block area 401 matches the written data information, and if the data read from the work block area 401 matches the written data information, step S342 is executed, and if the data read from the work block area 401 does not match the written data information, step S344 is executed.

And S342, acquiring and recording the time sequence information.

S343, determining whether the timing information of the storage device has been traversed, if so, performing step S345, and if not, performing step S344.

S344, adjust the timing information of the storage device to the next file, and re-execute step S341.

And S345, screening the recorded time sequence information to obtain the optimal reading time sequence information.

Referring to fig. 1, fig. 2, fig. 5 and fig. 6, in an embodiment of the present invention, in step S341, it is determined whether the read/write information of the work block area 401 is consistent by using an error correction code, and if the read/write information is consistent with the read/write information, the current timing information is available, so in step S342, the timing information of the storage device at this time is recorded. The recorded timing information includes column address access Time (CL), row address to column address Delay Time (tRCD), row address Strobe Precharge Time (tRP), and row address Active Time (trada address Strobe Time, traas). If the data information read from and written into the operation block area 401 is not consistent, it indicates that the current timing information is not suitable for the current memory device, and is not enough for the memory device to stably read information at the double data rate, so in step S344, the timing information of the memory device is adjusted to the next level, and the operation in step S341 is performed again to select the available timing information. Specifically, the Clock information of the storage device may be adjusted, such as a Command Per Clock (CPC) to boost the instruction rate of the storage device, a CL parameter, a tRP parameter, a tRCD parameter, a tRAS parameter, and the like. The method is applied to the aging test process, and can effectively avoid the influence on the test due to environment and equipment factors, so that the bad block rate is higher, and the problem of bad blocks caused by parameter problems is reduced as much as possible, thereby screening out the equipment bad blocks which can not be adjusted.

Referring to fig. 1, fig. 2, fig. 5 and fig. 6, in an embodiment of the present invention, after the current timing information is acquired and recorded in step S342, the operation of step S343 is executed to determine whether the timing information has been traversed. Specifically, the time sequence information of the storage device relates to multi-gear parameters, so that after the test of the time sequence of one gear is completed, the test of the time sequence of the next gear is performed, and the available time sequence information of the storage device is selected as much as possible, so that the measuring and calculating precision of the optimal read time sequence information is improved, and errors caused by random data value taking and errors caused by the test environment in the aging machine are reduced. Until all timing information has been tested, it is determined that the timing has been traversed, and step S345 may be performed. In this embodiment, the lowest gear, which is also the first gear with the highest comprehensive performance and the lowest fault-tolerant rate of the storage device, is selected as the initial gear of the timing information, and then the timing of the lowest gear is increased primarily until the first gear corresponding to the maximum rated parameter of the storage device is reached, so that the test can be stopped. In step S343, the criterion for determining may be to determine whether the current timing information is the maximum rated parameter, so as to stop the test. In step S345, the timing information selected in the above step is further selected, thereby obtaining optimum read timing information. Specifically, the intermediate value of the timing sequence information can be selected to improve the fault tolerance rate of parameter selection and reduce the error influence of random values. For example, the storage device may optionally be set to several gears 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 in Auto (Auto) mode. And after testing, several gear positions such as 1, 5, 6, 7 and 8 which can ensure that the storage device finishes data reading at double data rate are obtained, and 6 gear positions are selected as the optimal reading timing information. If the number of the gears is 5, 6, 7 and 8, the gear 6 or the gear 7 is selected as the optimal reading timing sequence information. The intermediate value refers to a median of the time sequence information, and is not an average value, so that the rapidity of adjusting the equipment in the aging test process is improved, the accuracy is high, the error interference of measurement and calculation can be eliminated, the parameter fault tolerance is improved, and the method is suitable for adjusting the equipment parameters in the aging test process.

Referring to fig. 1, fig. 2, fig. 5 and fig. 7, in an embodiment of the present invention, in step S35, the timing information of the storage device is adjusted to be the optimal read timing information, and then data is written into the work block area 401. In this case, the data written in the work block area 401 in step S34 may be erased first to free the work block area 401. After writing data to the work block area 401, data is read from the work block area 401, and the written data and the read data of the work block area 401 are compared. Specifically, step S35 includes steps S351 to S356.

S351, erasing the data in the working block area, and setting the read time sequence information as the optimal read time sequence information.

And S352, adjusting the time sequence information of the storage device, and writing and reading data into the work block area.

S353 determines whether the written data information matches the preset data information, if the read and written data information match, step S354 is executed, and if the read and written data information do not match, step S352 is executed.

S354, recording the current read timing information.

And S355, judging whether the timing information is traversed, if so, executing the step S356, and if not, executing the step S352.

And S356, acquiring the optimal read timing information.

Referring to fig. 1, fig. 2, fig. 5 and fig. 7, in step S351, the data written in step S34 is re-erased, and the read timing information is set as the optimal read timing information. In step S352, data is written into the work block area at the double data rate, and the written data is read out at the double data rate to determine whether the written data is consistent with the preset data information. The preset data information is data information to be written into the work block area 401. In step S353, it can be judged by the error correction code whether or not the data information read and written by the work block region 401 coincides. On the basis of correcting the read timing in step S34, if the read/write is consistent, the current timing information can ensure that the storage device reads/writes normally, and the operation in step S354 is executed to record the current read timing information. If the reading and writing are not consistent, the current timing information is not enough to support the memory device to write data at the double data rate, so the operation in step S352 is performed. Specifically, in step S352, the read timing information is shifted to the next stage, similarly to step S344. And traversing the time sequence information, and screening out the time sequence information which can enable the storage equipment to normally write data at double data rate. And in step S356, the optimum readout timing information is obtained by acquiring the intermediate value of the readout timing information. In this embodiment, the intermediate value refers to a median of the read timing information, so as to improve the efficiency of adjusting the parameters of the storage device in the burn-in machine.

Please refer to fig. 2, 5-7, it should be noted that in steps S34 and S35, the data written in the work block area 401 need not be written to the memory module 20, but only needs to be written randomly, so as to improve the testing efficiency, maintain the balance between the environmental factors and the testing process in the burn-in test, and obtain better testing effect. Through steps S31 to S35, the optimal read timing information and the optimal write timing information can be obtained, and the optimal read timing information and the optimal write timing information are set as standard parameters for testing, or the optimal read timing information and the optimal write timing information can be set as card-open parameters. The tuning of the parameters of the storage device is completed through the above step S30.

Referring to fig. 1-3, the content of step S40 in the testing method of the memory device according to the present invention is as follows.

And S40, performing a second read-write test on the working block area and the system block area according to the read-write parameter information, and marking a second bad block area in the working block area and the system block area according to the result of the second read-write test.

Referring to fig. 1-3 and 8, in an embodiment of the invention, after tuning the parameters, a more detailed test may be performed on the data area 40, specifically, a second read-write test may be performed on the work block area 401 to further screen out bad blocks. The step S40 specifically includes steps S41 to S43.

And S41, pretesting the working block area and the system block area.

And S42, performing a second read-write test on the working block area.

And S43, performing a second read-write test on the system block area.

Referring to fig. 1 to 3 and 8, in an embodiment of the present invention, in step S41, before performing formal testing on the work block area 401 and the system block area 50, the work block area 401 and the system block area 50 are predicted. Specifically, the data stored in the work block area 401 and the system block area 50 are erased, and the data are written into the work block area 401 and the system block area 50. The process of erasing data and writing data is repeated for a plurality of times, the work block area 401 and the system block area 50 are warmed, random errors in subsequent tests can be effectively reduced, and therefore the measurement accuracy in the step S42 and the step S43 can be improved conveniently. Specifically, in the memory block 30 to be tested, the data in the memory block 30 is erased, and then, for example, data "0" is written into all the memory pages of the memory block 30, and then, data "0" is read out from all the memory pages of the memory block 30, thereby completing the pretest. During the pre-test, no statistics and error detection are performed on the test.

Referring to fig. 1-3 and 8, in an embodiment of the invention, after the pretest is completed, a second read/write test is performed on the working block area 401. Wherein the second read-write test comprises: data stored in the work block area 401 is erased, data is written into the work block area 401, and data is read from the work block area 401. In the memory module 20, data is written to all the memory pages of the memory block 30 in the work block area 401. And then reads out data from all the memory pages of the memory block 30. The error reporting data of the ECC in the second read/write test is counted, and the storage block 30 with the error is recorded to form a set, and the set is used as the second bad block area 4023. The bad block flag information is stored in the result page of the storage block 30 according to the error reporting data of the ECC, and a bad block mapping table corresponding to the second bad block area 4023 is established in the bad block mapping table area 60, so as to avoid the subsequent use of the determined bad block. In this embodiment, for the flash memory chip 1, the flash memory granule 10 may be one of a Single-Level Cell (SLC), a Multi-Level Cell (MLC), and a Triple-Level Cell (TLC). When the flash memory chip 1 includes a plurality of flash memory particles 10, the single-level cells are tested first, and then the multi-level cells and the three-level cells are tested to order the test process. Each flash memory pellet is subjected to a second read-write test.

Referring to fig. 1-3, 8 and 9, in an embodiment of the invention, after the second read/write test on the working block area 401 is completed, in step S42, the read/write test is performed on the system block area 50. In this embodiment, the storage device is a flash memory chip 1, and the duty ratio of the working block area of the flash memory chip 1 can reach 90%, for example, so that the stability of the test can be ensured by testing the working block area 401 first. Specifically, step S42 includes steps S421 to S424.

And S421, editing the logic address of the system block area and dividing the system block area.

And S422, performing second read-write test on the parameter block, the code block and the power-on reset data transmission storage block.

And S423, marking and replacing the bad blocks in the system block area.

S424, a mapping relation between the bad blocks and the bad block is established in the bad block table mapping area, and the marked bad block set is used as a second bad block area.

Referring to fig. 1-3 and 8-10, in an embodiment of the invention, in a burn-in environment, each memory module 20 is divided to increase the testing efficiency. Specifically, a partial area in the memory module 20 is divided into a plurality of test sections. In the present embodiment, in step S421, the system block area 50 is divided into, for example, 2 test sections, which are a first test section 51 and a second test section 52, respectively. The first test section 51 and the second test section 52 may be implemented according to the logical address of the editing memory block 30. Specifically, the first test section 51 and the second test section 52 include the same number of memory blocks 30. In the system block area 50, a parameter block 501, a code block 502, and a power-on-reset data storage block 503 are defined in the system block area 50 according to the type of the storage information. The parameter block 501 is used to store parameter information during a test process, the code block 502 is used to store programming data, and the Power-On Reset data storage block 503 is used to store Power-On Reset (POR) related data. Specifically, the first test part 51 includes a first parameter block 5011, a first code block 5021 and a first power-on-reset data storage block 5031, and the second test part 52 includes a second parameter block 5012, a second code block 5022 and a second power-on-reset data storage block 5032. The test is carried out in first test part 51 and second test part 52, in the high temperature environment of aging test, can not only guarantee the stability of test, can also promote the efficiency of test.

Referring to fig. 1-3 and 8-10, in an embodiment of the invention, in step S422, a second read/write test is performed on the parameter block 501, the code block 502, and the power-on reset data transmission storage block 503. The test is grouped by two identical parameter blocks 501, two identical code blocks 502, and two identical power-on-reset-data-to-data-storage blocks 503. Wherein, the same refers to the storage size, the storage information type, the distribution structure of the storage blocks 30, and the same storage information, and two test structures in one group can form effective mutual backup between two tested blocks in the same group. The test procedure for each group is the same, and the following description will take the test of two identical parameter blocks 501 as an example to describe the second read/write test procedure in the system block area 50. First, the stored information in the first parameter block 5011 is erased, then the stored information in the second parameter block 5021 is written into the first parameter block 5011, and the error data during the storing process is recorded in the database of the aging tester. Next, the stored information in the second parameter block 5021 is erased, the stored information in the first parameter block 5011 is written into the second parameter block 5021, and the error data generated during the storage process is recorded in the database of the burn-in tester. The steps of the second read-write test are repeated in two code blocks 502 and two power-on-reset data-output storage blocks 503, again with error data recorded in the burn-in tester database. If the test process of the machine fails, the data of the test failure is stored in the database of the aging tester so as to facilitate the follow-up tracing.

Referring to fig. 1-3 and 8-10, in step S423, according to the error data generated during the second read/write test, bad blocks are marked in the system block area 50, and the set of bad blocks is divided into a second bad block area 4023. A good block is selected in the work block area 401 to replace the bad block detected in the system block area 50. Wherein if the parameter block 501 comprises a bad block. When replacing the parameter block 501, a new block of the replacement parameter block 501 is edited by the code block 502 so that it can directly replace the parameter block 501. Wherein the replacement of the block can be achieved by editing the logical address of the block. If the code block 502 comprises a bad block, the new block that replaces the code block 502 is to satisfy the storage search rules of a Read-Only Memory (ROM). In steps S421 to S423, a bad block located in the system block area 50 is selected and a bad block located in the data area 40 is finely screened, so that a second bad block area 4023 is formed. In step S424, the address of the second bad block area 4023 is recorded in the bad block table mapping area 60 to form a reference mapping so as not to use a bad block in the subsequent operation of the storage device.

Referring to fig. 1-3, through steps S10-S40, a first bad block area 4022 and a second bad block area 4023 are marked in a flash memory chip 1, and the first bad block area 4022 and the second bad block area 4023 are combined with an original factory bad block area 4021 to form a bad block area 402 in the flash memory chip 1. The bad block area 402 and the bad block table mapping area 60 have a mapping relationship. The content of step S50 in the method for testing a memory device according to the present invention is as follows.

And S50, obtaining the bad block information of the first bad block area and the second bad block area, and recording the bad block information in the bad block table mapping area.

Referring to fig. 1-3 and 11, in an embodiment of the invention, in step S50, the bad block table mapping area 60 is tested. The step 50 specifically includes steps S51 to S53.

And S51, editing the logic address of the bad block area, and dividing the bad block area into a plurality of first bad blocks and second bad blocks.

And S52, erasing the storage information of the first bad block, and updating the storage information of the first bad block according to the bad block information of the bad block area in the test process.

And S53, erasing the storage information of the second bad block, and writing the storage information of the first bad block into the second bad block.

Referring to fig. 1-3, 11 and 12, in an embodiment of the present invention, in step S51, the bad block area 402 is divided into a plurality of first bad blocks 4024 and second bad blocks 4025. The first bad blocks 4024 and the second bad blocks 4025 are equal in number, the original factory bad block area 4021 includes the first bad blocks 4024 and the second bad blocks 4025 which are equal in number, the first bad block area 4021 includes the first bad blocks 4024 and the second bad blocks 4025 which are equal in number, and the second bad block area 4021 includes the first bad blocks 4024 and the second bad blocks 4025 which are equal in number, so that a mutual backup data structure is formed between the first bad blocks 4024 and the second bad blocks 4025. In step S52, the storage information of the first bad block 4024 is erased, and the bad block information obtained by the test in steps S10 to S40 is written in the first bad block 4024. The bad block information includes a bad block address, bad block result page data, bad block timeout information, the number of error bits of the ECC code, the address of the poor-quality storage page 301, and the like. So that the corresponding information of the bad block can be read after power-on. In step S53, the storage information of the second bad block 4025 is erased, and the storage information of the first bad block 4024 is written in the second bad block 4025 to form backup data, thereby avoiding power-off redo. And storing the test result in a database of the aging tester. In step S50, if a failure alarm occurs in the storage process, the failure condition is recorded in the SBBT and is found in the storage module 20 from the storage block 30 of the last row of the address until the problem storage block 30 is determined.

Referring to fig. 1-12, in an embodiment of the invention, after the steps S10-S50 are executed, the data in the code block 502 is retained to avoid redoing the test after the system is powered on, and the data information stored in the flash memory chip 1 is erased to remove redundant information. In the test procedures from step S10 to step S50, the test criteria for determining a bad block may be set to various types. In this embodiment, the determination criteria of the bad block are, for example, that the block cannot be erased normally in the reading stage, the block cannot be programmed and written normally in the reading stage, the time for erasing the block does not conform to the set threshold range, the time for writing the block does not conform to the set threshold range, the number of Error bits of reading and writing is greater than the threshold set by the card opening, the number of Uncorrectable codes (Uncorrectable Error Correction Code) of reading is greater than, for example, 200/4000 bits, and the time for reading the block does not conform to the set threshold range, etc.

Referring to fig. 1-3 and 13, the present invention further provides a test system 70 for a storage device, where the test system 70 includes a partitioning module 701, a first read-write test module 702, a tuning module 703, a second read-write test module 704, and a profiling recording module 705. The partitioning module 701 is configured to establish the data area 40, the system block area 50, and the bad block table mapping area 60 in the storage device according to the type of the storage information. The first read-write testing module 702 is configured to perform a first read-write test on the data area 40, and establish a first bad block area 4022 and a working block area 401 in the data area 40 according to a result of the first read-write test. The tuning module 703 is configured to adjust timing information of the storage device, obtain read-write error information of the work block area 401, and repeatedly tune read-write parameter information of the storage device according to the read-write error information. The second read/write testing module 704 is configured to perform a second read/write test on the working block area 401 and the system block area 50 according to the read/write parameter information, and mark a second bad block area 4023 in the working block area 401 and the system block area 50 according to a result of the second read/write test. The profiling recording module 705 is configured to obtain bad block information of the first bad block area 4022 and the second bad block area 4023, and record the bad block information in the bad block table mapping area 60.

Referring to fig. 14, the present invention further provides a storage device, where the storage device includes a processor 80 and a memory 90, where the memory 90 stores program instructions, and the processor 80 executes the program instructions to implement the configuration method of the data model. The Processor 80 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component; the Memory 90 may include a Random Access Memory (RAM), and may also include a Non-Volatile Memory (Non-Volatile Memory), such as at least one disk Memory. The Memory 90 may also be an internal Memory of Random Access Memory (RAM) type, and the processor 80 and the Memory 90 may be integrated into one or more independent circuits or hardware, such as: application Specific Integrated Circuit (ASIC). It should be noted that the computer program stored in the memory 90 may be implemented in the form of software functional units and stored in a computer readable storage medium when the computer program is sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a storage device, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.

Referring to fig. 14, the present invention further provides a computer-readable storage medium 1001, wherein the computer-readable storage medium 1001 stores computer instructions 100, and the computer instructions 100 are used for causing the computer to execute the above-mentioned method for configuring a data model. The computer readable storage medium 1001 may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system or propagation medium. The computer-readable storage medium 1001 may also include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Optical disks may include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-RW), and DVD.

In summary, the present invention provides a test method and a test system for a storage device, and also provides a storage device loaded with the test system provided by the present invention. The test method divides the storage device into a data area, a system block area and a bad block table mapping area, carries out a first read-write test on the data area so as to mark a first bad block area and a working block area, tunes the read-write parameters of the storage device, carries out a second read-write test on the working block area and the system block area so as to mark a second bad block area, and finally processes the bad block table mapping area and the bad block area so as to record the bad block information and complete a complete bad block test process.

In the description of the present specification, reference to the description of the terms "present embodiment," "example," "specific example," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for testing a memory device, comprising:

2. The method of claim 1, wherein the step of tuning the read-write parameters of the memory device comprises:

3. The method of claim 2, wherein the step of tuning the read-write parameters of the memory device comprises:

4. The method as claimed in claim 1, wherein after repeatedly tuning the read/write parameter information of the storage device, searching a result page of a storage block in the storage device, and creating a bad block mapping table in the bad block mapping table area, wherein the bad block mapping table includes a bad block address and bad block information of the first bad block area.

5. The method for testing a memory device according to claim 1, wherein the step of performing the first read-write test comprises:

6. The method according to claim 1, wherein after the bad block mapping table is established, the storage device is pretested before the second read-write test.

7. The method for testing a memory device of claim 1, wherein the step of performing the second read-write test comprises:

erasing the storage information of the storage block to be tested;

writing data into all storage pages of the storage block to be tested; and

and reading all storage pages of the storage block to be tested.

8. The method of claim 1, wherein the step of marking the second bad block area comprises:

editing a logic address of the system block area, and establishing a first test part and a second test part in the system block area;

9. The method of claim 8, wherein the step of marking the second bad block area comprises: and in the process of the second read-write test, the storage information of the first test part and the second test part is backed up and stored mutually.

10. The method of claim 8, wherein the step of establishing the first test portion and the second test portion comprises:

11. A system for testing a storage device, comprising:

the second read-write testing module is used for carrying out second read-write testing on the working block area and the system block area according to the read-write parameter information and marking a second bad block area in the working block area and the system block area according to the result of the second read-write testing; and

12. A storage device, characterized in that the storage device has stored thereon a computer program which, when being executed by a processor, implements the method of testing a storage device according to claim 1.