CN117250470A

CN117250470A - Chip testing method, testing device, electronic equipment and storage medium

Info

Publication number: CN117250470A
Application number: CN202210656990.9A
Authority: CN
Inventors: 李彬彬; 屈志; 朱皖江
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-06-10
Filing date: 2022-06-10
Publication date: 2023-12-19

Abstract

The embodiment of the disclosure provides a chip testing method, a chip testing device, electronic equipment and a storage medium. The method comprises the following steps: executing a first test on the chip based on the first test list, and acquiring a test result of the first test; the first test list includes a plurality of test items; based on the failed test item in the test result of the first test, performing repair operation on the chip corresponding to the failed test item; and executing a second test on the repaired chip based on the failure test item.

Description

Chip testing method, testing device, electronic equipment and storage medium

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular, to a method and a device for testing a chip, an electronic device, and a storage medium.

Background

With the increasing application range of semiconductor chips, the scale of semiconductor chip design is also increasing, and highly complex semiconductor chips are facing increasingly serious challenges such as high reliability, high quality, low cost, and shorter product market period. Moreover, as semiconductor process dimensions shrink, there are more and more types of failures that may exist in a chip. The chip test can effectively find out the failed chip and repair the failed chip so as to improve the product yield. Chip testing is therefore critical to semiconductor chip design and production.

However, when the chip is tested by the current chip testing method, the testing time is longer and the testing cost is higher.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a method, an apparatus, an electronic device, and a storage medium for testing a chip to solve at least one problem existing in the prior art.

In order to achieve the above object, the technical solution of the embodiments of the present disclosure is implemented as follows:

a first aspect of an embodiment of the present disclosure provides a method for testing a chip, the method including: executing a first test on the chip based on the first test list, and acquiring a test result of the first test; the first test list includes a plurality of test items;

based on the failed test item in the test result of the first test, performing repair operation on the chip corresponding to the failed test item;

and executing a second test on the repaired chip based on the failure test item.

In some embodiments, the test conditions of the first test and the test conditions of the second test are different.

In some embodiments, before the performing, based on the failed test item in the test result of the first test, a repair operation on the chip corresponding to the failed test item, the method further includes: generating a failure item list based on failure test items in the test result of the first test; the failure item list comprises the test number of the failure test item, the position of the chip corresponding to the failure test item and the failure address corresponding to the failure test item.

In some embodiments, the performing a repair operation on the chip corresponding to the failed test item based on the failed test item in the test result of the first test includes: and executing the repair operation on the chip corresponding to the failure test item based on the failure item list.

In some embodiments, the performing a second test on the repaired chip based on the failure test item includes: performing a second test on the patched chip based on the failure item list and a second test list; the test items in the second test list are identical to the test items in the first test list.

In some embodiments, the performing a second test on the patched chip based on the failure item list and a second test list includes: judging whether the test items in the second test list are failure test items in the failure item list or not; and if the test item in the second test list is the failure test item in the failure item list, executing a second test on the repaired chip based on the test item.

In some embodiments, the performing a second test on the patched chip based on the failure term list and the second test list further includes: and if the test item in the second test list is not the failed test item in the failed test item list, skipping the test item.

In some embodiments, after the performing a second test on the patched chip based on the failure test term, the method further comprises: and if the test results of all the test items in the second test are passed, determining that the test result of the repaired chip is qualified.

A second aspect of embodiments of the present disclosure provides a test apparatus for a chip, the apparatus including: the first test module is used for executing a first test on the chip based on the first test list and acquiring a test result of the first test; the first test list includes a plurality of test items; the repair module is used for executing repair operation on the chip corresponding to the failed test item based on the failed test item in the test result of the first test; and the second test module is used for executing a second test on the repaired chip based on the failure test item.

In some embodiments, the first test module is further to: generating a failure item list based on failure test items in the test result of the first test; the failure item list comprises the test number of the failure test item, the position of the chip corresponding to the failure test item and the failure address corresponding to the failure test item.

In some embodiments, the patching module is specifically configured to: and executing the repair operation on the chip corresponding to the failure test item based on the failure item list.

In some embodiments, the second test module is specifically configured to: performing a second test on the patched chip based on the failure item list and a second test list; the test items in the second test list are identical to the test items in the first test list.

In some embodiments, the second test module is specifically configured to: judging whether the test items in the second test list are failure test items in the failure item list or not; and if the test item in the second test list is the failure test item in the failure item list, executing a second test on the repaired chip based on the test item.

In some embodiments, the second test module is specifically configured to: and if the test item in the second test list is not the failed test item in the failed test item list, skipping the test item.

In some embodiments, the apparatus further comprises a determination module for: and if the test results of all the test items in the second test are passed, determining that the test result of the repaired chip is qualified.

A third aspect of the disclosed embodiments provides an electronic device comprising a memory, a processor and a computer program stored on the memory, which when executed by the processor, implements the steps of the above method.

A fourth aspect of the disclosed embodiments provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the above method.

The embodiment of the disclosure provides a chip testing method, a chip testing device, electronic equipment and a storage medium. The method comprises the following steps: executing a first test on the chip based on the first test list, and acquiring a test result of the first test; the first test list includes a plurality of test items; based on the failed test item in the test result of the first test, performing repair operation on the chip corresponding to the failed test item; and executing a second test on the repaired chip based on the failure test item. The method and the device can avoid repeated testing of the passing test items in the first test by executing the second test on the repaired chip based on the failed test items in the test results of the first test, and can reduce the test time and the test cost because the failed test items in the test results of the first test are tested in the second test.

Drawings

Fig. 1 is a flow chart of a method for testing a chip according to an embodiment of the disclosure;

fig. 2 is a specific flow chart of a method for testing a chip according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of test results of a first test provided by an embodiment of the present disclosure;

FIG. 4a is a partial schematic diagram of a first test failure term list provided by an embodiment of the present disclosure;

FIG. 4b is a partial schematic view of a test time list for a first test provided by an embodiment of the present disclosure;

FIG. 5a is a partial schematic diagram of a list of failed items for a second test provided by an embodiment of the present disclosure;

FIG. 5b is a partial schematic view of a test time list for a second test provided by an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a testing device for a chip according to an embodiment of the disclosure;

fig. 7 is a hardware configuration diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be appreciated that spatially relative terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In general, when testing a chip, a first test is performed on the chip to be tested, then the chip to be tested is repaired based on the test item whose test result is fail (fail) in the first test, and then a second test is performed on each test item of each chip to be tested under a looser test condition. Wherein the test items of the first test are the same as the test items of the second test. That is, whether the test item fails or not in the first test, a second test is performed based on the test item. Therefore, the test efficiency is lower, the test time is longer, and the test cost is higher.

Fig. 1 is a flow chart of a testing method of a chip according to an embodiment of the disclosure. As shown in fig. 1, in step 101, a first test is performed on a chip based on a first test list, and a test result of the first test is obtained.

The present disclosure is not limited to the type of chip, and in some embodiments, the chip may be a memory chip, and in particular, the chip may be a volatile memory chip including random access memory (Random Access Memory, RAM), dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM), etc., or the chip may be a nonvolatile memory chip including NAND flash memory, NOR flash memory, or resistance variable memory. In other embodiments, the chip may also be a non-memory chip, such as a logic chip or the like.

The first test list comprises a plurality of test items (items), each test item corresponds to different test contents, and corresponding performance tests can be carried out on the chip so as to meet the production requirements of the chip. By way of example, the test items may be a row refresh time (Row Refresh Cycle Time, TRFC) test, a row-to-column address delay time (RAS to CAS Delay Time, TRCD) test, a precharge time (RAS Precharge Time, TRP) test, a write recovery time (Write Recovery Time, TWR) test, a data input/output test, a high temperature test, a low temperature test, a burn-in test, or a wear-out test, etc., although not limited thereto, and only examples specifically recited herein are provided for ease of understanding, and it should be understood that any chip performance test item is intended to be encompassed by the present disclosure. In some embodiments, the first test may be performed on multiple chips at the same time, and it should be noted that the first test lists corresponding to different chips may be the same or different.

In some embodiments, ATE (Automatic Test Equipment, automated test equipment) is employed to perform testing on chips. For each test item, a test vector (pattern) corresponding to the test item may be generated by a computer and sent to the ATE, and then the ATE inputs the test vector to the chip under test, or the ATE directly generates the test vector and inputs the test vector to the chip under test. The chip under test may generate test data based on the test vector, and determine whether the test result of the test item is fail (fail) by determining whether the test data is consistent with the original test vector. The generated test data may be exclusive-ored with the original test vector to generate a test result indication signal. For example, if the test result indication signal is 1, it indicates that the generated test data is inconsistent with the original test vector, that is, the test result of the test item is failure, that is, the test item is a failure test item; if the test result indication signal is 0, the generated test data is consistent with the original test vector, that is, the test result of the test item is passing, that is, the test item is passing. The test result of the first test may include a test result indication signal corresponding to each test item.

In step 102, a repair operation is performed on a chip corresponding to a failed test item based on the failed test item in the test results of the first test.

Here, for each test item in the first test list, if the test result of the test item is detected to be failed, the test item is determined to be a failed test item.

In some embodiments, the repair operation may be performed on the chip corresponding to the failed test item by a repair circuit preset in the chip. The repair circuit may perform a repair operation on the chip based on each failure test term to improve product yield. Illustratively, for DRAM chips, it typically includes a memory array and repair circuitry. The memory array includes a plurality of memory cells for implementing the storage of data. The repair circuit includes a plurality of spare memory cells for replacing failed memory cells in the memory array. And by determining the position of the failed storage unit, the failed storage unit is replaced by the standby storage unit in the repair circuit. The replacement referred to herein is to replace the address of the failed memory cell with the spare address corresponding to the spare memory cell. Specifically, the spare decoding logic corresponding to the spare memory cell is set to the replacement decoding state of the corresponding faulty memory cell by blowing the word line or bit line of the decoder corresponding to the faulty memory cell, and simultaneously by fuse programming, so as to replace the address of the faulty memory cell with the spare address of the spare memory cell in the repair circuit.

In step 103, a second test is performed on the repaired chip based on the failed test item.

In the embodiments of the present disclosure, the test conditions for the second test are different from the test conditions for the first test. In some embodiments, the second test may be performed under more relaxed conditions than the first test, e.g., the first test may be performed at a temperature in excess of room temperature (greater than 30℃. Or less than 0℃.), the second test may be performed at room temperature (e.g., 0-30℃.), or the first test may be performed at a temperature above the standard operating voltage of the chip, and the second test may be performed at the standard operating voltage of the chip.

According to the embodiment of the disclosure, the second test is executed on the repaired chip based on the failed test item in the test result of the first test, so that repeated test on the passing test item in the test result of the first test in the second test process can be avoided. In addition, since the test conditions of the second test are more relaxed than those of the first test, that is, the test items which can pass the test in the first test can pass the test in the second test, the pass test items in the test result of the first test are not tested again in the second test, and the accuracy of the test result is not affected. The method and the device execute the second test on the repaired chip based on the failure test item in the test result of the first test, so that the test time and the test cost can be reduced and the test efficiency can be improved on the basis of not affecting the accuracy of the test result. Moreover, the present disclosure may test a plurality of chips simultaneously, and for each chip to be tested, performing a second test on the chip based on its failed test item in the test result of the first test may greatly reduce the test time and test cost of all chips.

Fig. 2 is a specific flow chart of a testing method of a chip according to an embodiment of the disclosure. As shown in fig. 2, in step 201, a first test is performed on a chip based on a test item in a first test list, and a test result of the test item is obtained.

Illustratively, fig. 3 is a schematic diagram of test results of a first test provided by an embodiment of the present disclosure. Each Test item in the first Test list has its corresponding Test number test_no and Test Name test_name, and each Test item in the first Test list may be tested for the first time in order of the Test numbers from small to large, for example, each Test item in the first Test list may be tested for the first time in order of the Test numbers from 1 to n. And simultaneously, recording the corresponding test result. As shown in fig. 3, for example, if the test result of the current test item is pass, the test item is recorded as pass test item NF (for example, test item with test number 2); if the test result of the current test item is failure, the test item is recorded as a failed test item F (for example, test item with test number 1), and meanwhile, the position of the chip corresponding to the failed test item, the failure address (fail address) of the failed test item, and the like may also be recorded. The failure address refers to the specific location of the circuit that caused the test item to fail. For example, the test item test failure may be due to a failure of a portion of the memory cells in the chip, and the failure address may be a row/column address corresponding to the failed memory cell.

In step 202, it is determined whether the first test has been completed.

In some embodiments, all test items in the first test list need to be tested for the first time, so if all test items in the first test list have been tested for the first time, it is determined that the first test is completed, and step 203 is performed; if there are some test items in the first test list that are not tested for the first time, it is determined that the first test is not completed, and the execution step 201 is returned, and the first test is executed on the chip based on the test items in the first test list that are not tested for the first time, and the test result of the test items is obtained.

In other embodiments, not all the test items in the first test list need be tested for the first time, but only the selected test items in the first test list need be tested for the first time, and the unselected test items in the first test list need not be tested for the first time, so if all the selected test items in the first test list have been tested for the first time, it is determined that the first test is completed, and step 203 is performed; if there are some selected test items in the first test list that are not tested for the first time, it is determined that the first test is not completed, and the execution step 201 is returned, and the first test is executed based on the selected test items in the first test list that are not tested for the first time, and the test result of the selected test items is obtained.

In step 203, a list of failed items is generated based on the failed test items in the test results of the first test.

Here, the fail item list (FB file) includes a test number of the fail test item, a location of a chip corresponding to the fail test item, and a fail address corresponding to the fail test item. In some embodiments, the list of failed items may also include the test names of the failed test items.

In some embodiments, in the testing process of each test item, if the test item is determined to be a failed test item, the test number of the failed test item, the position of the chip corresponding to the failed test item, the failure address corresponding to the failed test item, and other information are directly recorded into the failure item list. In other embodiments, during the testing of each test item, whether the test item is a pass test item or a fail test item, its corresponding test result is recorded in the first test result list. For example, in the first test result list, for passing test items, only the corresponding test numbers thereof are recorded, while for failing test items, the corresponding test numbers thereof, the positions of the chips, and the failure addresses are recorded. A list of failed items is then generated based on the failed test items in the first test result list.

FIG. 4a is a partial schematic diagram of a first test failure term list provided by an embodiment of the present disclosure. As shown in fig. 4a, the list of failed items for the first test includes a test number, a corresponding chip location, and a corresponding failure address for each failed test item in the first test. In the first test, a plurality of chips may be tested simultaneously. The test items that need to be performed by different chips may be the same or different. The same failure test item may correspond to multiple chips, e.g., failure test item number 303 corresponds to multiple different chip locations. That is, the test results of test item test number 303 were all failed during the first test of chips 6-4, 6-7, 6-21, 6-57, and 6-65. The same fail test item may also correspond to multiple fail addresses of the same chip, i.e., multiple circuits at different locations cause the test item to fail, e.g., fail test item test number 572 corresponds to multiple different fail addresses of the same chip. In some embodiments, multiple tests may be performed by writing different values for the same test item of the same chip. It should be noted that for test items that do not appear in the failed item list, it may be either pass test items or unselected test items in the first test list.

In other embodiments, for each test item in the first test list, the test result of the first test further includes a test time (test time), and the test time of each test item is recorded in the test time list. Fig. 4b is a partial schematic diagram of a test time list for a first test provided by an embodiment of the present disclosure. As shown in fig. 4b, each test item has its corresponding test number and test name, and "BH" in the test name of the test item indicates the first test. The test vector time (pattern time) refers to the time of applying test vectors to the chip to be tested, and the test vectors corresponding to different test items are different, so that the corresponding test vector times are also different. In some embodiments, the host computer sends test commands to the ATE to control the ATE to perform test operations on the chip under test. The data processing time (data time) refers to the time for the upper computer to process data, for example, the time for the upper computer to process test results. Test item time refers to the sum of test vector time and data processing time. It should be noted that the test vector time, the data processing time, and the test item time are all results that retain three bits after the decimal point. Referring to FIG. 4b, for test items 568 and 570, the corresponding test vector time is 0, which indicates that test items 568 and 570 were not tested in the first test, i.e., test items 568 and 570 were unselected test items in the first test list.

Referring to fig. 4a and 4b, test items with test numbers 569 and 577 correspond to test vector times of 18.374s and 0.373s, respectively, that is, test items with test numbers 569 and 577 were tested in the first test, but test items with test numbers 569 and 577 did not appear in the failure item list shown in fig. 4 a. It is known that test items with test numbers 569 and 577 are pass test items.

Returning to FIG. 2, in step 204, a repair operation is performed on the chip corresponding to the failed test item based on the list of failed items. And aiming at the test number, the corresponding chip position and the corresponding failure address of each failure test item in the failure item list, the repair operation is carried out on the chip, so that the yield of the chip can be improved to a certain extent. In some embodiments, a portion of the circuitry that caused the test item to fail is replaced with repair circuitry preset in the chip to perform the repair operation.

After performing the repair operation on the chip, a second test is performed on the repaired chip based on the failure item list and the second test list. In step 205, it is determined whether the test item in the second test list is a failed test item in the failed item list. In some embodiments, the test items in the second test list are the same as the test items in the first test list, and the information in the second test list may be the same as the information in the first test list; in other embodiments, the test items in the second test list are identical to the test items in the first test list, but the information in the second test list is different from the information in the first test list, specifically: for the same test item, the test number of the test item in the second test list may be different from the test number of the test item in the first test list.

If the current test item in the second test list is not the failed test item in the failed test item list, step 206 is performed, the test item is skipped, and step 208 is performed continuously to determine whether the second test is completed.

In some embodiments, the second test list may also be matched with the same test item in the first test list to determine whether the current test item in the second test list is a failed test item in the failed item list.

If the current test item in the second test list is a failed test item in the failed test item list, step 207 is executed to perform a second test on the repaired chip based on the failed test item. It should be understood that the method of the second test is similar to that of the first test, and thus will not be described in detail. Then, step 208 is performed to determine whether the second test is complete.

In some embodiments, all test items in the second test list need to determine if they are failed test items in the failed item list. Therefore, if all the test items in the second test list have already been executed in step 205, it is determined that the second test is completed, and step 209 is executed; if there are some test items in the second test list that have not been executed in step 205, it is determined that the second test is not completed, and step 205 is executed in a return manner, and it is determined whether the test items in the second test list that have not been executed in step 205 are failed test items in the failed item list.

In other embodiments, not all of the test items in the second test list need to determine whether they are failed test items in the failed item list, but only selected test items in the second test list need to determine whether they are failed test items in the failed item list. Therefore, if all the selected test items in the second test list have been executed in step 205, it is determined that the second test is completed, and step 209 is executed; if there are some selected test items in the second test list that have not been executed in step 205, it is determined that the second test is not completed, and step 205 is executed in a return manner, and it is determined whether the selected test items in the second test list that have not been executed in step 205 are failed test items in the failed item list.

In the embodiment of the disclosure, the second test is performed on the repaired chip based on the failure item list and the second test list. In other embodiments, a second test may be performed on the patched chip directly based on the list of failure terms. That is, the second test is directly performed on the repaired chip based on each failure test item in the failure item list until all failure test items in the failure item list have been subjected to the second test, and then the second test is judged to be completed, and the step 209 is further performed, and the test result of the repaired chip is output.

In step 209, the test result of the repaired chip is output. If the test results of all the test items in the second test are passed, judging that the test result of the repaired chip is qualified; if the test result of the test item in the second test is failure, judging that the test result of the repaired chip is unqualified. In the second test, if the test result of the test item is failure, it is indicated that the test item cannot be repaired successfully in step 203, so as to determine that the test result of the repaired chip is failed.

In some embodiments, after performing a second test on the repaired chip based on the test item for each test item, if the test item is a failed test item, the test number of the failed test item, the location of the corresponding chip, and the corresponding failure address are recorded in a failure item list to generate a failure item list for the second test. In addition, for each test item, after the second test is performed on the repaired chip based on the test item, whether or not it is a failed test item, the test time of the test item is recorded in the test time list to generate a test time list of the second test.

FIG. 5a is a partial schematic diagram of a list of failed items for a second test provided by an embodiment of the present disclosure. The list of failed items for the second test in FIG. 5a is similar to the list of failed items for the first test in FIG. 4a, including the test number, corresponding chip location, and corresponding failure address for each failed test item in the second test.

Fig. 5b is a partial schematic view of a test time list for a second test provided by an embodiment of the present disclosure. The test time list of the second test in fig. 5b is similar to the test time list of the first test in fig. 4b, each test item has its corresponding test number and test name, and "AH" in the test name of the test item indicates the second test. It should be noted that the test vector time, the data processing time, and the test item time are all results that retain three bits after the decimal point.

Referring to fig. 4a to 5b, the test item with test number 869 in fig. 5b is the same test item (test name trfc_check) as the test item with test number 569 in fig. 4b, and the test item with test number 877 in fig. 5b is the same test item (test name RPAP) as the test item with test number 577 in fig. 4 b. As described above, the test items under test names trfc_check and RPAP (test items under test numbers 569 and 577) are pass test items in the first test, and therefore, in the second test, the second test is not performed on the test items under test names trfc_check and RPAP (test items under test numbers 869 and 877). As shown in FIG. 5b, the test vector times for test items numbered 869 and 877 are each 0, so the test item times for test items numbered 869 and 877 also include only the respective data processing times (e.g., the time taken to determine that the test item is not a failed test item in the failed item list of the first test and skip the test item). Therefore, the method and the device can avoid repeated testing of the passing test items in the test result of the first test by executing the second test on the repaired chip based on the failed test items in the test result of the first test, thereby reducing the test time and the test cost and improving the test efficiency.

Fig. 6 is a schematic diagram of a testing apparatus for a chip according to an embodiment of the disclosure. As shown in fig. 6, the testing apparatus 600 includes a first testing module 601, a repairing module 602, and a second testing module 603. The first test module 601 is configured to perform a first test on the chip based on the first test list, and obtain a test result of the first test; the first test list includes a plurality of test items; the repair module 602 is configured to perform a repair operation on a chip corresponding to a failed test item based on the failed test item in the test result of the first test; the second test module 603 is configured to perform a second test on the repaired chip based on the failure test item.

In some embodiments, the first test module 601 is further configured to generate a failure term list based on the failed test terms in the test result of the first test; the failure item list comprises the test number of the failure test item, the position of the chip corresponding to the failure test item and the failure address corresponding to the failure test item.

In some embodiments, the patching module 602 is specifically configured to perform a patching operation on a chip corresponding to a failed test item based on a list of failed items.

In some embodiments, the second test module 603 is specifically configured to perform a second test on the patched chip based on the failure term list and the second test list; the test items in the second test list are identical to the test items in the first test list.

In some embodiments, the second test module 603 is specifically configured to: judging whether the test items in the second test list are failure test items in the failure item list or not; if the test item in the second test list is a failed test item in the failed test item list, a second test is performed on the repaired chip based on the test item.

In some embodiments, the second test module 603 is specifically configured to: if the test item in the second test list is not the failed test item in the failed test item list, skipping the test item.

In some embodiments, the test apparatus 600 further comprises a determination module 604. The determining module 604 is configured to: if the test results of all the test items in the second test are passed, determining that the test result of the repaired chip is qualified.

Fig. 7 is a hardware configuration diagram of an electronic device according to an embodiment of the present disclosure. As shown in fig. 7, the electronic device 700 includes: at least one processor 701 and memory 702; optionally, the electronic device 700 may further comprise at least one communication interface 703; the various components in the electronic device 700 may be coupled together by a bus system 704, with the understanding that the bus system 704 is used to enable connected communications between the components. The bus system 704 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration, the various buses are labeled as bus system 704 in fig. 7.

It is to be appreciated that the memory 702 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. The memory 702 is used to store various types of data to support the operation of the electronic device 700. Examples of such data include: any computer program for operating on the electronic device 700, a program implementing the methods of embodiments of the present disclosure, may be contained in the memory 702.

The test method of the chip disclosed in the embodiments of the present disclosure may be applied to the processor 701 or implemented by the processor 701. The processor 701 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 701 or by instructions in the form of software. The processor 701 may be a general purpose processor, a digital signal processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 701 may implement or perform the methods, steps, and logic blocks of the disclosed embodiments. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method in connection with the embodiments of the present disclosure may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a storage medium in a memory 702. The processor 701 reads information in the memory 702 and, in combination with its hardware, performs the steps of the method as described above.

In an exemplary embodiment, the electronic device 700 can be implemented by one or more application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic devices (Programmable Logic Device, PLD), complex programmable logic devices (Complex Programmable Logic Device, CPLD), field-programmable gate arrays (Field-Programmable Gate Array, FPGA), general purpose processors, controllers, microcontrollers (Micro Controller Unit, MCU), microprocessors (Microprocessor), or other electronic components for performing the methods described above.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.

The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purposes of the embodiments of the present disclosure.

In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.

The disclosed embodiments also provide a computer storage medium having stored thereon a computer program which, when executed by at least one processor, performs the steps of the method of testing a chip described above. The computer readable storage medium may be a magnetic random access Memory (Ferromagnetic Random Acces s Memory, FRAM), read Only Memory (ROM), programmable Read Only Memory (Programmable Read-Only Memory, PROM), erasable programmable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable programmable Read Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or compact disk Read Only Memory (Compact Disc Rea d-Only Memory, CD-ROM).

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for testing a chip, the method comprising:

executing a first test on the chip based on the first test list, and acquiring a test result of the first test; the first test list includes a plurality of test items;

2. The method of testing a chip according to claim 1, wherein the test conditions of the first test and the test conditions of the second test are different.

3. The method according to claim 1, wherein the method further comprises, before performing a repair operation on the chip corresponding to the failed test item based on the failed test item in the test results of the first test:

generating a failure item list based on failure test items in the test result of the first test; the failure item list comprises the test number of the failure test item, the position of the chip corresponding to the failure test item and the failure address corresponding to the failure test item.

4. The method according to claim 3, wherein the performing a repair operation on the chip corresponding to the failed test item based on the failed test item in the test result of the first test includes:

and executing the repair operation on the chip corresponding to the failure test item based on the failure item list.

5. The method of claim 3, wherein performing a second test on the repaired chip based on the failure test item comprises:

performing a second test on the patched chip based on the failure item list and a second test list; the test items in the second test list are identical to the test items in the first test list.

6. The method of claim 5, wherein performing a second test on the patched chip based on the failure term list and a second test list comprises:

judging whether the test items in the second test list are failure test items in the failure item list or not;

and if the test item in the second test list is the failure test item in the failure item list, executing a second test on the repaired chip based on the test item.

7. The method of testing a chip according to claim 6, wherein the performing a second test on the patched chip based on the failure item list and a second test list, further comprises:

and if the test item in the second test list is not the failed test item in the failed test item list, skipping the test item.

8. The method of testing a chip according to claim 1, wherein after the performing of the second test on the repaired chip based on the failure test item, the method further comprises:

and if the test results of all the test items in the second test are passed, determining that the test result of the repaired chip is qualified.

9. A test apparatus for a chip, the apparatus comprising:

the first test module is used for executing a first test on the chip based on the first test list and acquiring a test result of the first test; the first test list includes a plurality of test items;

the repair module is used for executing repair operation on the chip corresponding to the failed test item based on the failed test item in the test result of the first test;

And the second test module is used for executing a second test on the repaired chip based on the failure test item.

10. The apparatus according to claim 9, wherein the test conditions of the first test and the test conditions of the second test are different.

11. The device for testing a chip according to claim 9, wherein the first testing module is further configured to:

12. The device for testing a chip according to claim 11, wherein the repair module is specifically configured to:

13. The device for testing a chip according to claim 11, wherein the second testing module is specifically configured to:

14. The device for testing a chip according to claim 13, wherein the second testing module is specifically configured to:

15. The device for testing a chip according to claim 14, wherein the second testing module is specifically configured to:

16. The apparatus according to claim 9, further comprising a determining module for:

17. An electronic device comprising a memory, a processor and a computer program stored on the memory, characterized in that the computer program when executed by the processor implements the steps of the method of any of claims 1 to 8.

18. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 8.