CN116312710A - Method for analyzing high NAND read-out error number - Google Patents

Method for analyzing high NAND read-out error number Download PDF

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Publication number
CN116312710A
CN116312710A CN202310286167.8A CN202310286167A CN116312710A CN 116312710 A CN116312710 A CN 116312710A CN 202310286167 A CN202310286167 A CN 202310286167A CN 116312710 A CN116312710 A CN 116312710A
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nand
read
analyzing
frequency
write
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CN202310286167.8A
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蒋书斌
曹成
李瑞东
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Shandong Sinochip Semiconductors Co Ltd
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Shandong Sinochip Semiconductors Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

A method for analyzing the high number of NAND read-out errors includes such steps as analyzing the problem of NAND channel from low frequency, eliminating interference from other factors, and determining whether it is the reason of welding, hardware circuit, hardware engineering, etc. And then analyzing whether the problem is a high-frequency problem, a software code problem or a NAND characteristic problem, so that the efficiency of analyzing and checking the problem is improved.

Description

Method for analyzing high NAND read-out error number
Technical Field
The invention relates to the technical field of memories, in particular to a method for analyzing high NAND read-out error number.
Background
The NAND Flash is a nonvolatile memory, power-down data is not lost, the size is small, and low-cost and high-efficiency large-capacity storage can be realized, so that the NAND Flash is widely applied.
In general, a NAND Flash has a plurality of chip select signals (CE), each of which is composed of a plurality of blocks (blocks) each including a plurality of Word lines (Word lines) each including a plurality of pages (pages). The user can Erase (Erase), write (Write) and Read (Read) operations on NAND Flash, where a Block is typically the smallest addressed unit of Erase operation, a Word line is typically the smallest addressed unit of Write operation, and a Page is typically the smallest addressed unit of Read operation.
When NAND Flash reads data, it is considerably different from the written data. On the one hand, due to the internal principle and the limitation of the manufacturing process, the situation of Bit (Bit) inversion can occur in the use process, namely, when the written data is read, some bits are changed from 1 to 0, and some bits are changed from 0 to 1. On the other hand, other causes are also possible.
Disclosure of Invention
In order to overcome the defects of the technology, the invention provides a method for conveniently checking the read-out errors of the NAND memory.
The technical scheme adopted for overcoming the technical problems is as follows:
a method of analyzing a high number of NAND read errors, comprising the steps of:
a) Testing the NAND access under the low-frequency environment, judging whether the NAND access is in hardware failure or not if the NAND access is not tested normally under the low-frequency environment, and executing the step b) if the NAND access is tested normally under the low-frequency environment;
b) Testing the NAND channel under the high-frequency environment, judging whether the hardware circuit supports high frequency or whether the NAND is configured under the high frequency if the NAND channel test under the high-frequency environment is abnormal, and executing the step c if the NAND channel test under the high-frequency environment is normal;
c) Analyzing whether the NAND erasing and reading process has a problem, and executing the step d) if the NAND erasing and reading process has no problem;
d) Whether or not the voltage axis is offset due to the NAND characteristic is analyzed.
Further, in step a), the read-write Register or the read-write Array or the read Register is performed on any Block of each chip select signal CE of the NAND at the frequency of 200Mbps or less, so as to complete the channel test.
Further, the hardware fault in step a) is a welding fault and/or a hardware circuit fault and/or a hardware engineering fault.
Further, in the step a), the operation of reading and writing Register or reading and writing Array or writing Array and reading Register is performed on any Block of each chip select signal CE of NAND by using 50Mbps frequency, so as to complete the channel test.
Further, in step b), at the frequency that the number of NAND read errors cannot meet the LDPC error correction requirement, any Block of each chip select signal CE of NAND performs a read-write Register or read-write Array or write Array, or read-Register operation.
Further, the NAND in step b) is configured as ZQ calibration and/or DCC Training and/or Write/Read DQ Training of the NAND at high frequencies.
Further, the step of analyzing whether the NAND erasing and reading process has a problem in the step c) is as follows: c-1) judging whether Erase is wiped clean or not, including whether the Erase forgets to exit from SLC mode, whether SLC erasure is performed or not, and whether the power supply voltage is insufficient or not;
c-2) checking Program disorder by printing WL and page numbers of each write on the Program;
c-3) checking the sequence of erasing, writing, reading or state checking operation after grabbing the waveform by using a logic analyzer, and comparing the sequence with a NAND manual to judge whether the sequence is correct or not;
c-4) adding printing check when executing normal erasing and reading commands each time, and judging whether other commands are added outside the normal operation flow;
c-5) judging whether the status check is correctly performed after the erasing and reading operation according to the printing status value.
Further, in step d), the command of obtaining the optimal reading voltage axis through NAND is used to obtain the optimal reading voltage axis, and the relative left bias or the relative right bias of the voltage axis is analyzed.
Further, in step d), an optimal reading voltage axis is found through a Shift Read command, and the relative left bias or the relative right bias of the voltage axis is analyzed.
Further, the method for searching the optimal reading voltage axis through the Shift Read command comprises the following steps: the other voltage axis offset is set to 0, the current page voltage axis is Read using the Shift Read command with a step size of 2 from negative offset 32 to positive offset 32, and the lowest error count is the current page optimal Read voltage axis.
The beneficial effects of the invention are as follows: the problem of NAND access is analyzed from low frequency, so that interference of other factors can be eliminated, and whether the problem is caused by hardware aspects such as welding, hardware circuits, hardware engineering and the like is determined. And then analyzing whether the problem is a high-frequency problem, a software code problem or a NAND characteristic problem, so that the efficiency of analyzing and checking the problem is improved.
Drawings
FIG. 1 is a schematic of a NAND architecture;
fig. 2 is a flow chart of the method of the present invention.
Detailed Description
The invention is further described with reference to fig. 1 and 2.
A method of analyzing a high number of NAND read errors, comprising the steps of:
a) And (c) testing the NAND access under the low-frequency environment, judging whether the NAND access is in hardware failure or not if the NAND access is not in normal under the low-frequency environment, and executing the step (b) if the NAND access is in normal under the low-frequency environment.
b) And C) testing the NAND channel in a high-frequency environment, judging whether the hardware circuit supports high frequency or whether the NAND is configured well in the high frequency if the NAND channel test in the high-frequency environment is abnormal, and executing the step C if the NAND channel test in the high-frequency environment is normal.
c) Analyzing whether the NAND erasing and reading process has a problem, and executing the step d) if the NAND erasing and reading process has no problem.
d) Whether or not the voltage axis is offset due to the NAND characteristic is analyzed.
The method for analyzing the NAND read-out error number is characterized in that whether the NAND read-out error number is a NAND access problem is analyzed from low frequency, so that interference of other factors can be eliminated, and whether the NAND read-out error number is a hardware reason such as welding, a hardware circuit, hardware engineering and the like is determined. And then analyzing whether the problem is a high-frequency problem, a software code problem or a NAND characteristic problem, so that the efficiency of analyzing and checking the problem is improved.
In one embodiment of the present invention, in step a), the read-write Register or the read-write Array or the read Register is performed on any Block of each chip select signal CE of NAND at a frequency of 200Mbps or less, thereby completing the channel test. Further preferably, the access test is completed by performing read-write Register or read-write Array or read Register operation on any one Block of each chip select signal CE of NAND using a frequency of 50 Mbps.
In one embodiment of the invention, the hardware fault in step a) is a welding fault and/or a hardware circuit fault and/or a hardware engineering fault.
In one embodiment of the present invention, in step b), at a frequency that the number of NAND read errors cannot meet the LDPC error correction requirement actually occurs, any one Block of each chip select signal CE of NAND performs a read-write Register or read-write Array or write Array, read-Register operation.
In one embodiment of the invention, the NAND configuration in step b) is ZQ calibration and/or DCC Training and/or Write/Read DQ Training of the NAND at high frequency, and a determination is made as to whether the configuration is well configured.
In one embodiment of the present invention, the step of analyzing whether the NAND erasing and reading process has a problem in the step c) is as follows:
c-1) judging whether Erase is wiped clean or not, including whether SLC mode is forgotten to be exited, whether SLC erasure is performed or not, whether power supply voltage is insufficient or not, and reading NAND after erasure can be conducted to check the data at the moment.
c-2) looking at Program out-of-order by programmatically printing WL and page numbers for each write.
c-3) checking the sequence of erasing, writing, reading or state checking operation after grabbing the waveform by using a logic analyzer, and comparing the sequence with the NAND manual to judge whether the sequence is correct or not.
c-4) adding print check each time a normal erase-write command is executed, judging whether other commands are added outside the normal operation flow (for example, entering SLC or setfeature);
c-5) judging whether the status check is correctly performed after the erasing and reading operation according to the printing status value.
In one embodiment of the present invention, the command to obtain the optimal read voltage axis through NAND in step d) obtains the optimal read voltage axis, and analyzes the relative left bias or the relative right bias of the voltage axis.
In one embodiment of the invention, in step d) the optimum Read voltage axis is found by a Shift Read command, and the relative left or right bias of the voltage axis is analyzed.
In one embodiment of the present invention, the method for searching the optimal Read voltage axis through the Shift Read command is as follows: the other voltage axis offsets are set to 0, the current Page (Page) voltage axis is Read from negative offset 32 to positive offset 32 in steps of 2, specifically-32, -30, -28, … …, 0, … …, 30, 32, using the Shift Read command, and the lowest error number is the current Page (Page) optimal Read voltage axis. Looking for reasons that may cause such an offset, in general, retention and OpenBlock will bias the voltage axis left and Read disturb will bias the voltage axis right.
Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A method of analyzing a high number of NAND read errors, comprising the steps of:
a) Testing the NAND access under the low-frequency environment, judging whether the NAND access is in hardware failure or not if the NAND access is not tested normally under the low-frequency environment, and executing the step b) if the NAND access is tested normally under the low-frequency environment;
b) Testing the NAND channel under the high-frequency environment, judging whether the hardware circuit supports high frequency or whether the NAND is configured under the high frequency if the NAND channel test under the high-frequency environment is abnormal, and executing the step c if the NAND channel test under the high-frequency environment is normal;
c) Analyzing whether the NAND erasing and reading process has a problem, and executing the step d) if the NAND erasing and reading process has no problem;
d) Whether or not the voltage axis is offset due to the NAND characteristic is analyzed.
2. The method of analyzing a high number of NAND read errors as claimed in claim 1, wherein: in the step a), the random Block of each chip selection signal CE of the NAND is subjected to read-write Register or read-write Array or write Array and read Register operation at the frequency of 200Mbps or below to complete the access test.
3. The method of analyzing a high number of NAND read errors as claimed in claim 1, wherein: the hardware fault in step a) is a welding fault and/or a hardware circuit fault and/or a hardware engineering fault.
4. The method of analyzing a high number of NAND read errors as claimed in claim 1, wherein: in the step a), the 50Mbps frequency is used for performing read-write Register or read-write Array or write Array and read Register operation on any Block of each chip select signal CE of the NAND, so as to complete the access test.
5. The method of analyzing a high number of NAND read errors as claimed in claim 2, wherein: in the step b), at the frequency that the number of NAND read-out errors cannot meet the LDPC error correction requirement, any Block of each chip selection signal CE of the NAND performs read-write Register or read-write Array or read-write Register operation.
6. The method of analyzing a high number of NAND read errors as claimed in claim 1, wherein: the NAND in step b) is configured as ZQ calibration and/or DCC Training and/or Write/Read DQ Training of the NAND at high frequency.
7. The method for analyzing a high number of NAND read errors as claimed in claim 1, wherein the step of analyzing whether the NAND erase-read process is problematic in step c) comprises:
c-1) judging whether Erase is wiped clean or not, including whether the Erase forgets to exit from SLC mode, whether SLC erasure is performed or not, and whether the power supply voltage is insufficient or not;
c-2) checking Program disorder by printing WL and page numbers of each write on the Program; c-3) checking the sequence of erasing, writing, reading or state checking operation after grabbing the waveform by using a logic analyzer, and comparing the sequence with a NAND manual to judge whether the sequence is correct or not;
c-4) adding printing check when executing normal erasing and reading commands each time, and judging whether other commands are added outside the normal operation flow;
c-5) judging whether the status check is correctly performed after the erasing and reading operation according to the printing status value.
8. The method of analyzing a high number of NAND read errors as claimed in claim 1, wherein: in the step d), the command of the optimal reading voltage axis is obtained through NAND, and the relative left bias or the relative right bias of the voltage axis is analyzed.
9. The method of analyzing a high number of NAND read errors as claimed in claim 1, wherein: in the step d), the optimal reading voltage axis is searched through a Shift Read command, and the relative left bias or the relative right bias of the voltage axis is analyzed.
10. The method of analyzing a high number of NAND Read errors as claimed in claim 9, wherein the method of finding the optimum Read voltage axis by Shift Read command is: the other voltage axis offset is set to 0, the current page voltage axis is Read using the Shift Read command with a step size of 2 from negative offset 32 to positive offset 32, and the lowest error count is the current page optimal Read voltage axis.
CN202310286167.8A 2023-03-20 2023-03-20 Method for analyzing high NAND read-out error number Pending CN116312710A (en)

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Application Number Priority Date Filing Date Title
CN202310286167.8A CN116312710A (en) 2023-03-20 2023-03-20 Method for analyzing high NAND read-out error number

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310286167.8A CN116312710A (en) 2023-03-20 2023-03-20 Method for analyzing high NAND read-out error number

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CN116312710A true CN116312710A (en) 2023-06-23

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