JPH0831197A - Dynamic random access memory - Google Patents

Abstract

PURPOSE:To perform mode switching in a short time by applying super Vcc to a specific pin and performing WCBR cycle, preventing mis-entry by a user by shifting from a normal mode to a vendor test mode, and unnecessitating applying Vcc after entry. CONSTITUTION:Super Vcc is applied to a specific pin, and WCBR cycle is performed. Shifting to a vendor test mode is specified by a data group address key given to an address pin at this time. Once, performing entry for a vender test mode, applying super Vcc is needless. Also, when it is reset to the test mode previously decided during entry, retuned to the normal mode. In the other entry system, entry conditions for the vendor test are same as in the past, WCBR cycle is performed for entry for a second level mode by only specifying the address key, and applying super Vcc is needless. In order to return to a submode from a sub-mode, WCBR cycle may be performed by giving the specific address key. The same way is performed to return to the normal mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory IC, and more particularly to a technique for facilitating switching of test modes of a semiconductor memory IC.

[0002]

2. Description of the Related Art Generally, a semiconductor memory is tested by using a dedicated tester called a tester to execute a data read cycle or write cycle on the semiconductor memory to be tested. It is to check whether or not the memory operates normally to determine whether or not the semiconductor memory is a normal product.

Prior to the description of the conventional technique, a structure of a DRAM (dynamic random access memory) as a semiconductor memory to be tested and its main operation cycle will be described with reference to the drawings.

FIG. 17 shows an example of the structure of a DRAM. DR
The data storage portion of the AM is a memory cell array in which cells for data storage (configured using capacitors) are two-dimensionally arranged. The "storage / retrieval" of data to / from this memory cell is performed by designating and selecting a desired memory cell by designating a row-direction address (referred to as "row address") and a column-direction address (referred to as "column address"). It is done by doing.

In a DRAM, a common address pin is usually used to specify a row address and a column address. A RAS (row address strobe) signal and a CAS (column address strobe) signal are used to distinguish whether the address data indicated by the address pin indicates a row address or a column address.

The fall of the RAS signal (transition from the high level to the low level) means that the address data indicated by the address pin specifies the row address, and the fall of the CAS signal. Means that the address data indicated by the address pin specifies a column address.

As shown in FIG. 17, as signals for controlling the operation of the semiconductor input from the outside, there are a RAS signal, a CAS signal, and a WE (write enable) signal. The WE signal indicates a read operation when the signal is at a high level, and a write operation when the signal is at a low level.

FIG. 19 shows a more detailed configuration example around the memory cell array.

As shown in FIG. 19A, the memory cell array and its peripheral circuits are composed of memory cells arranged two-dimensionally, word lines and bit lines connecting the memory cells vertically and horizontally, and row address latches. A word line driver 42 that drives the voltage of the corresponding word line to a high level according to the result of decoding by the decoding circuit, and a sense amplifier that amplifies the voltage read from the memory cell to the bit line, which is connected to the bit line. 43, a selection circuit 44 for selecting the corresponding bit line according to the decoding result by the column address latch / decode circuit. A booster circuit 41 described later is also provided.

FIG. 19B shows a circuit example of one memory cell. Each memory cell is configured to have a cell capacitance (capacitor) 45, which is a minute capacitance for storing data, and a gate switch 46 for reading the content held in the cell capacitance 45 onto a bit line. There is.

When a word line is driven by a high level voltage, each gate switch 46 connected to the word line concerned.
Is turned on, and the content held in the corresponding cell capacitor 45 is read onto each bit line.

As a result, a minute voltage change appears on the bit line, and the sense amplifier 43 amplifies this voltage change and detects it as a low level voltage or a high level voltage.

In FIG. 19A, the booster circuit 41 supplying the voltage to the word line driver 42 is a circuit having a function of making the drive voltage of the word line higher than the power supply voltage.

This is because the gate drive voltage is equal to the threshold of the gate switch 46 so that the voltage drop does not occur due to the ON operation of the gate switch 46 for electrically connecting the cell capacitance 45 and the bit line. It is for boosting pressure and is a generally known means.

FIG. 18 shows a normal operation cycle of the DRAM.

These cycles will be described with reference to FIGS. 17, 18 and 19.

In the DRAM read cycle, first, WE
This is executed by setting (write enable (a signal of active low as shown in the figure): signal indicating a write cycle) to a high level (inactive). Next, add the row address (row address) to the address pin (Fig. 17).
And the RAS signal is fallen, the row address is taken into the row address latch / decode circuit. Thus, due to the fall of the RAS signal,
When the row address is fetched by the internal row address latch / decode circuit (FIG. 17) and address decoding is started, the word line corresponding to this address is boosted by the word line driver (FIGS. 19 and 42). 1
It is driven so as to have the high level voltage boosted in (9, 41).

A gate switch (FIG. 1) connected to the word line driven to have the high level voltage.
9, 46) each turned on and the corresponding cell capacity 45
Will be output to the corresponding bit line.
Then, the operation of the sense amplifier (FIGS. 19 and 43) is started, a minute voltage change in the bit line is amplified, and the voltage of the bit line is set to the high level or the low level.

Further, the address pin (FIG. 17)
A column address (column address) is applied to the column address and the CAS signal is made to fall, so that the column address is taken into the column address latch / decode circuit. According to the decoding result by the column address latch / decode circuit,
The selection circuit (FIGS. 19 and 44) selects the sense amplifier 43 of the corresponding bit line, and the data input / output buffer (FIG. 1).
7) via the data I / O pin (Fig. 17)
Output the data.

Next, the write cycle of the DRAM is WE
This is executed by setting (write enable) to Low level (active). The data to be written is given to the data I / O pin.

Hereinafter, the row address is applied to the address pin to cause the RAS signal to fall, then the column address is applied to cause the CAS to fall, as in the write cycle.

The internal operation of the DRAM at this time is basically similar to the write cycle, but the write data given to the data I / O pin is applied to the bit line designated by the column address. The difference is that data is written in the cell capacitance connected by the gate switch.

As described above, the operation cycle of the DRAM is
It is distinguished by the operation patterns of three signals of RAS, CAS and WE. In normal read and write cycles, R
The signal changes in the order that the AS signal first falls and then the CAS signal falls, but this order is changed in the refresh cycle.

In the cycle shown in FIG. 8A, the CAS signal first falls, and then the RAS signal falls. This cycle is usually CBR (CAS
This is called a before RAS) cycle, which instructs the DRAM to execute a refresh cycle.

In the CBR cycle, the WE signal is inactive (high level). On the other hand, as shown in FIG. 8B, a state in which the CAS signal is lowered before the RAS signal while WE is kept active (low level) is called a WCBR cycle. Normally, this cycle is used. Not done.

In the cycle shown in FIG. 9, after the RAS signal is dropped, the R signal is output without dropping the CAS signal.
This is a cycle in which the AS signal is returned to its original state, which is a refresh cycle called RAS on recycle.

RAS pin, CAS pin, and W
From the signal given to the E pin, the RAS signal (row control signal), CAS signal (column control signal),
And WE (buffer control signal) are generated by
The control circuit, as shown in FIG.

Since the general circuit configuration and operation cycle of the DRAM have been described above, the prior art of the test support function of the DRAM, which is the object of the present invention, will be described below.

The test time of the semiconductor memory is exponentially long as the capacity of the semiconductor memory to be tested is increased. Therefore, in a DRAM having a capacity of 1 Mbit or more, the memory Functions that support examinations have become built-in.

As a typical example of this test support function,
There is a parallel bit test function. When this function is selected, the contents of multiple bits are
The data is read out in parallel inside the M chip, and a match / mismatch between the data of the plurality of bits is determined by internal hardware, and the determination result is output to a predetermined data pin.

For example, as shown in FIG. 15, if 4-bit parallel comparison is internally performed and this function is selected, "4M
In a DRAM having a storage capacity of “× 1 (bit)”,
The test can be performed as a DRAM having a storage capacity of 1M, which is the address depth of "1/4", and the test time can be greatly reduced.

Such a test support function is used, for example, in a device maker at the time of a memory shipment selection test, and is not used when a general user operates as a normal memory. Therefore, such a test support function (hereinafter referred to as "test mode") specifies a cycle that is not possible when using a normal memory operation so that a general user does not accidentally start it. By doing so, it is supposed to be started.

As described above, the test mode is originally provided for reducing the test cost in the device maker, but the above-mentioned parallel bit test function or the like makes the memory compatible with the system developed by the user. After incorporating
If it can be used for failure diagnosis of the system, it will be useful for the user.

Therefore, among the test modes, the one that is effective for the user is open to the general user as the "standard open test mode" under the agreement of each manufacturer. Such a "standard open test mode" is generally a WCBR (write enable pin) so that it can be activated within the range that can be activated even after the memory is installed in the system, and that it does not accidentally activate during normal operation of the memory. While activating WE, CAS before RAS is performed).

On the other hand, there is also a test mode in which each device maker independently incorporates it in the memory and does not disclose it to the user. This test mode is referred to as the "vendor test mode" in contrast to the "standard disclosure test mode". I am calling it.

In the "vendor test mode", a complicated activation (hereinafter referred to as "entry") condition shown in FIG. 2 is adopted because of its non-disclosure nature, and an erroneous entry by the user is prevented.

That is, as shown in FIG. 2, the vendor test mode can be entered from the normal mode (normal use mode) only when a complicated starting condition is satisfied.
That is, any one of mode 1, mode 2 and mode 3 can be entered. There is a test function corresponding to each mode. For example, mode 1 is a mode corresponding to the parallel bit test function.

Further, the transition from the vendor test mode to the normal mode is performed by, for example, the above-mentioned CBR cycle,
It is performed by RAS on recycling.

An example of the complicated starting condition will be described.

To enter the "vendor test mode", a WCBR cycle is performed with a super Vcc (voltage higher than the power supply voltage) applied to a predetermined specific pin (for example, the highest pin of an address). I have to do it. As described above, by applying the application of the super Vcc to a specific pin as one of the entry conditions for the "vendor test mode", the memory IC is incorporated into the system developed by the user to enter the vendor test mode. Making entry impossible. The address key in the figure is data given to the address pin in order to determine which of the existing modes is to be entered, and it is set in advance. In the example of FIG. 2, in order to distinguish mode 1, mode 2 and mode 3,
It is sufficient that there is at least 2-bit address data.

[0041]

Before explaining the problem to be solved by the present invention, referring to FIG. 2 which is a transition diagram of the operation mode to the vendor test mode, the conventional method for entering the vendor test mode is described. Will be explained. Figure 2
On the left side, the normal mode, which is a normal memory operation mode, is shown on the left side, and the vendor test mode is shown on the right side. Normally, memory is used in normal mode,
In order to enter the vendor test mode from this state, it is necessary to satisfy the entry condition provided to prevent erroneous entry. When this condition is satisfied, the operation mode can be transited through the thick line barrier shown in FIG.

In order to satisfy the entry condition, as shown in the figure, the WCBR cycle is executed while applying the super Vcc to the predetermined pin, and the address pin has the predetermined address ( It is necessary to give the address key).

This address key has a plurality of vendor test modes (in FIG. 2, as an example, mode 1, mode 2,
It is used to specify which of the three modes (mode 3) exists).
When the vendor test mode is entered, the vendor test mode can be reset and the normal mode can be restored by executing the above-mentioned CBR cycle or RAS on-recycle. As described above, normally, in order to enter the vendor test mode, it is necessary to specify a specific address key and execute the WCBR cycle while applying a super Vcc (voltage higher than the power supply voltage) to a specific pin. Need to do.

This is effective for preventing erroneous entry by the user as described above, but when the vendor test mode is used during the test, it takes a long time to enter the test mode as compared with the normal operation cycle of the device. Therefore, there is a problem that the test time becomes long. this is,
This is because when entering the vendor test mode, it is necessary to switch the voltage level on the side of the test apparatus that applies the super Vcc to the specific pin, and it takes a long time to change this voltage level. It should be noted that the lengthening of the test time progresses further with the dramatic increase in the memory capacity, which is a big problem.

Hereinafter, this problem will be described in detail with reference to FIGS.

FIG. 3 shows a general procedure for a memory test using the vendor test mode.

Here, the problem is the labor (time for testing) to enter the vendor test mode, and the content of the vendor test mode itself is not an essential problem. Therefore, it is simply shown here as a "special test" in the vendor test mode, and its contents will not be described in particular.

In the test shown in FIG. 3, first, data "0" is written from the address "0" of the memory to be tested to the maximum address to initialize all the memory cells.

Subsequently, the addresses "0" to the maximum address are sequentially focused on, and for each focused address,
After writing the inverted data of the initialization data (the inverted data of the data “0” is “1”), the “special test” is performed in the test mode and the normal test is performed in the normal mode.

This completes all the tests using the initialization data "0". Then, the same test is performed again using the data "1" as the initialization data, and all the tests are completed.

That is, in this test, first, initialization data “0” is tested by using its inverted data “1”, and then initialization data “1” is inverted by its inverted data. The test using "0" is performed again.

The above test will be described in detail with reference to the flowchart of FIG.

First, in step 1 of FIG. 3, the test data is set to 0. This is because "0" is used as the initialization data.

The processing from step 2 to step 5 is
To prepare for the test, test data (“0”) is written to all addresses to initialize all memory cells.

The processing from step 6 to step 13 is the processing of the test main body, and the test is performed while sequentially setting the addresses 0 to the maximum address as the addresses of interest.

First, in step 6, the address of interest is set to "0", and this address of interest is processed in step 7
Perform the tests from to 11
Then, the address of interest is updated (the address of interest is increased by 1), and finally the branch to step 7 in step 13 executes the test for all addresses.

In this way, the test is executed while sequentially changing the address of interest.

First, in step 7, the inversion data of the initialization data is written to the address of interest, and the contents of the address of interest and the contents of other addresses are in an inversion relationship (inversion relationship: "0"). "1" and "1" have a relationship of "0").

Here, in step 8, the vendor test mode is entered, and in step 9, a special test is carried out. As for the contents of this special test,
For example, forcibly lower the internal word line drive voltage,
For example, it is possible to perform read / write in a state where there is no operation margin, and to verify whether the data retention / storage function as a memory is guaranteed.

Then, in step 10, the vendor test mode is exited, and in step 11, a test in the normal operation mode is performed.

In step 12, the data indicated by the address of interest is returned from the inverted data to the original initialization data (test data), and then the content of the address of interest is incremented to update the address of interest. Further, in step 13, the process returns to step 7 and the above-described test is continued until the test for the maximum address (MAX address) which is the maximum value of the address is completed. It should be noted that in step 15, since the processing is performed on the initialization data 1, the process branches to step 2 only for the first time.

The above is the general procedure of the test using the vendor test mode.

By the way, in the test example shown here, it is necessary to perform entry into the vendor test mode every time the address of interest is updated. Therefore, the address depth n
When a word memory (memory having addresses 0 to n−1) is used as a test target, the number of times the process of each step is executed is once because step 1 is only executed at the start of the test. , Step 2 is executed at the beginning of each of the initialization data “0” and the initialization data “1”, so a total of two times, Steps 3 to 5
For each of the two types of initialization data (0, 1),
Since all addresses are repeated, 2n times each, step 6 twice, steps 7 to 13 2n times each,
Steps 14 and 15 will each be performed twice.

In the case of a memory having a normal capacity, step 8 which is a step for entering the vendor test mode
Occupies about 10% of the total number of execution steps. However, although Step 8 is about 10% in terms of the number of executions, the execution time of other steps (100 (ns)
To about 200 (ns)), it takes a long time (on the order of 10 (ms)) for the execution time, so that most of the actual test time was required. The reason why it takes time to enter the vendor test mode will be described while explaining the operation of the tester for testing the memory.

Hereinafter, with reference to FIG. 14 which is a block diagram of the tester and FIG. 4 which is an operation flowchart of the tester, what operation the tester performs during entry control of the memory to be tested into the test mode. I will explain.

FIG. 14 shows a schematic structure of a tester used for testing a memory. The tester includes a tester main body (measurement unit) having a function of generating an applied waveform to be applied to the memory to be tested and determining a response waveform from the memory to be tested, and a tester CPU which is a processing unit for controlling the main body. Configured to have.

The tester body further generates a test timing generator for generating the rising / falling timing of the test waveform and the timing for judging the response waveform, and the address, data and control signals (WE signal etc.) used for the test. Test pattern generator, a function to set the applied voltage to the memory under test to a high level voltage or a low level voltage, and a function to set a threshold voltage for judging the normality of the response waveform from the memory under test. A voltage setting device and a waveform for applying a predetermined test pattern signal (address, data / control signal, etc.) generated by these devices to a memory under test at a predetermined voltage level at a predetermined timing ( "Waveform generator" performs),
The response waveform from the memory under test is compared with a predetermined threshold voltage, converted into logical data, and at a predetermined timing,
It is configured to have pin electronics having a function of comparing with predetermined expected value data (performed by the “waveform judging device”).

The above timings, patterns, voltage levels, etc. are set by the tester CPU by writing data in a setting register (not shown) of the tester body. Further, the operator creates a program for moving the tester CPU so that the tester CPU writes desired data in the setting register of the tester main body.

FIG. 4 shows in detail the flow of processing during entry control to the vendor test mode in step 8 shown in FIG. 3 using the tester as described above.

In FIG. 4, time elapses from the top to the bottom of the figure.

First, as shown in the figure, it is assumed that the tester main body is performing a read or write operation (a write operation in step 7 shown in FIG. 3) with respect to a normal mode test target memory. Next, in order to enter the test target memory into the vendor test mode, the tester main body (measurement unit) suspends the test operation and interrupts the tester CPU.

The tester CPU determines the cause of the interrupt, activates the handler routine for performing the corresponding process,
Instruct the voltage setter to change the DC level (DC voltage level) of the pin electronics of the tester body (measuring section) (the hardware section that actually generates the waveform to be applied to the memory under test), and The super Vcc can be applied to a specific pin (for example, the most significant pin of the address). Here, the tester CPU waits for a predetermined time, and waits for an operation until the changed voltage level becomes stable. After the level is stabilized, the tester CPU instructs the tester main body (measuring unit) to restart the test operation.

The tester main body is
The WCBR cycle is executed while applying the super Vcc. As a result, the memory under test enters the vendor test mode. Here, since the tester body restores the DC level of pin electronics,
The operation is temporarily stopped again, and the tester CPU is interrupted.

The tester CPU activates the interrupt handler routine, restores the DC level of the pin electronics to the original level, waits for the level to stabilize, and then instructs the tester body to restart the operation.

The tester main body performs a special test (step 9 in FIG. 3) on the test target memory that has entered the test mode. As described above, the operation of applying the super Vcc includes the operation of temporarily stopping the tester main body, interrupting the tester CPU, changing the DC level, and waiting until the DC level stabilizes. The operation requires an extremely long time as compared with the operation cycle of.

FIG. 5 shows the operating times of these cycles for comparison.

FIG. 5A shows a normal operation cycle, and time passes from left to right in the figure. Figure 5
One break shown in (a) indicates one operation cycle, and the test in the normal mode is as shown in the figure.
For example, every 120 (ns), the operation cycle continues one after another.

In FIG. 3, except for the step 8 in which the test mode is entered, the processing in the other steps can be executed in a time of the operation cycle time of the memory under test. Taking a DRAM as an example, this operation cycle is generally about 120 (ns) as shown in FIG. Further, FIG. 5B shows a cycle including an entry to the test mode, one delimiter shows one operation cycle similarly to FIG. 5A, and time is from the left in the drawing. Pass to the right. In the normal mode, a write operation or the like can be executed at 120 (ns), but the mode switching (entry) requires the processing described in FIG. Then, the voltage level of the applied waveform to the specific pin is changed to the super Vcc level, and after executing the WCBR cycle of 120 (ns), it takes 10 (ms) time again to change the voltage level of the applied waveform to It has returned to the normal level.

As described above, the entry into the vendor test mode is about 10% of all the test steps in terms of the number of executions in the general test procedure shown in FIG.
It will account for most of the time spent running all tests.
That is, for entry into vendor test mode,
There is a problem that the test time may increase to 1000 times or more of the original test time.

Therefore, if the modes are repeatedly switched during the test, the test time can be significantly increased if the condition of "applying the super Vcc to a specific pin" can be excluded from the entry condition of the vendor test mode. Although it can be shortened, this is similar to the "standard public test mode", and there is a possibility that the user may enter the private test mode.

Therefore, an object of the present invention is to reduce the test time even if a test in which the mode is repeatedly repeated is performed while preventing the user from mistakenly making an erroneous entry in the vendor test mode. It is to provide a means that does not grow.

[0082]

In order to solve the above problems, the following means are considered.

That is, a dynamic random access memory (DRA) in which memory cells are arranged in a matrix.
In M), a plurality of address pins that receive a signal that specifies a memory address, a plurality of data pins that receive data to be read from and written to the DRAM, and a light that receives a first digital signal to enable writing of data to the memory. A second digital signal for accepting a second digital signal for enabling the signals given to the enable (WE) pin and the address pin to be read as a signal for designating the position of the memory cells arranged in a matrix in the row direction Row Adress storo
be: RAS) pin and a signal applied to the address pin, a third digital signal for receiving a signal for designating a column-direction position of memory cells arranged in a matrix is accepted. Column address strobe (CAS) pin,
In order to execute a plurality of types of tests on the DRAM from the outside of the DRAM, a test circuit that sets the state inside the DRAM to a predetermined state that is predetermined according to the type of the test and a first predetermined condition are provided. When satisfied, a test mode existing among a plurality of existing test modes is entered into a test mode that is associated in advance with a pattern of a signal applied to an address pin, and a DRAM from outside the DRAM that is associated with the test mode is entered. In order to enable the execution of the test for the
When the second predetermined condition is satisfied and the second predetermined condition is satisfied, a test preliminarily associated with the pattern of the signal applied to the address pin from the currently entered test mode is satisfied. A test mode circuit for entering the mode and activating the test circuit to enable execution of a new test on the DRAM from outside the DRAM associated with the test mode.

Then, the test mode circuit is connected to the WE
A case where the second digital signal is applied to the RAS pin after the third digital signal is applied to the CAS pin in a state where the first digital signal is applied to the pin, It is determined that the first predetermined condition is satisfied when a voltage (super Vcc voltage) of a predetermined value or more is applied to a pin specified in advance among the address pin and the data pin. Then, in the state in which the first digital signal is applied to the WE pin and the first entry portion that enters the test mode according to the pattern of the signal applied to the address pin, the C
After the third digital signal is applied to the AS pin,
When the second digital signal is applied to the RAS pin, it is determined that the second predetermined condition is satisfied, and a second entry unit for entering a test mode according to the pattern of the signal applied to the address pin. And a configuration with.

Other modes are also possible.

That is, a dynamic random access memory (DRA) in which memory cells are arranged in a matrix.
In M), a plurality of address pins that receive a signal that specifies a memory address, a plurality of data pins that receive data to be read from and written to the DRAM, and a light that receives a first digital signal to enable writing of data to the memory. A second predetermined digital signal for enabling the signals applied to the enable (WE) pin and the address pin to be read as a signal for specifying the row-direction position of the memory cells arranged in a matrix. Accepts Row Address Strobe
strobe: RAS) pin and a signal applied to the address pin as a third predetermined digital signal for enabling the reading of a signal designating the position of the memory cells arranged in a matrix in the column direction. Column address strobe (CA)
S) pin, and a test circuit that sets the internal state of the DRAM to a predetermined state according to the type of the test in order to execute a plurality of types of tests on the DRAM from outside the DRAM. When a predetermined condition is satisfied, a sub-base mode, which is a mode including a plurality of test modes, is entered, and when a second predetermined condition is satisfied, one sub-base mode is configured. DR entered in a test mode previously associated with the pattern of the signal applied to the address pin and associated with the test mode
A test mode circuit for activating the test circuit that enables the DRAM to execute a test from the outside of the AM.

Then, the test mode circuit is connected to the WE
A case where the second digital signal is applied to the RAS pin after the third digital signal is applied to the CAS pin in the state where the first digital signal is applied to the pin, To any of the address pins and the data pins that are specified in advance,
A voltage (super Vcc voltage) higher than a predetermined value is applied,
Furthermore, the pattern of the signal given to the address pin is
When the signal pattern given to the predetermined address pin matches, it is determined that the first predetermined condition is satisfied, and the first entry unit that enters the sub-base mode and the first digital signal on the WE pin. When the second digital signal is applied to the RAS pin after the third digital signal is applied to the CAS pin while the signal is applied, the second predetermined condition is satisfied. And a second entry section for entering the test mode according to the pattern of the signal applied to the address pin.

[0088]

In order to solve the above-mentioned problems, the present invention is provided with means for eliminating the need to apply the super Vcc only when switching between the vendor test modes. That is, in order to enter the vendor test mode from the normal mode, the "super Vcc + WCBR cycle" as in the conventional case is performed,
In addition, it is necessary to enter the address key,
The entry (switching) to the other mode from the state where the entry is made in any one of the modes can be performed only by executing the WCBR cycle, and the application of the super Vcc is unnecessary.

This situation is shown in FIG. 1 (a). Similar to the description of FIG. 2, FIG. 1A shows a state of transition between operation modes of the memory. Normally, the normal mode is entered, but to enter any of the modes belonging to the vendor test mode, the super Vcc is applied to a specific pin, the WCBR is further executed, and the address key is input. I do. When one of the vendor test modes is entered, the transition from that vendor test mode to another vendor test mode is performed by the condition indicated by the thick dotted line (WCBR cycle + address key transition shown in FIG. 1A). It is possible only by satisfying the specification of the destination mode.

As another means, as shown in FIG. 1B, the vendor test mode is divided into two levels, and the entry condition from the normal mode to the vendor test mode is the same as the conventional one. The entry from the first level mode to the second level mode is "WCBR cycle +
Only the "address key" is used, and the super Vcc is unnecessary.

As a result, in both the first level mode and the second level mode, it is necessary to once apply the super Vcc and execute the WCBR cycle to make an entry. The erroneous entry prevention function can be maintained.

Further, among the test modes, the test mode that requires frequent switching during the test is the second level mode, and the mode switching is performed between the first level and the second level.
By doing this between the level and the first level, frequent test mode switching (corresponding to step 8 and step 10 in FIG. 3) at the time of test is performed except when the first level mode is entered. As shown in the figure, since the super Vcc is not necessary, the test time is not lengthened.

The basic difference between FIGS. 1A and 1B is that, in FIG. 1A, if one of the vendor test modes is entered, the switching between the modes can be arbitrarily performed. In (b), switching between the vendor test modes is limited to only a specific mode of the first level mode called a sub-base mode and any one of the second level modes. is there. However, in either case, the entry condition from the normal mode to the vendor test mode is the same as the conventional one, and the entry to the vendor test mode is performed while preventing the erroneous entry by the user, and the other vendor test mode is entered. “Applying super Vcc to a specific pin”
By eliminating the requirement, the test time can be significantly reduced.

As described above, in order to enter the normal mode to the vendor test mode, it is necessary to apply the super Vcc to the specific pin to execute the WCBR cycle. That is, the conventional entry method shown in FIG. The function of preventing an erroneous entry from the user can be maintained as in the conventional case. Further, the point that is essentially different from the conventional technique is that the super Vcc is not required for the switching operation between the modes after once entering the vendor test mode. Therefore, the switching operation between the modes can be performed only by the time required for the WCBR cycle, and the test time can be greatly shortened while maintaining the conventional erroneous entry prevention function.

[0095]

Embodiments of the present invention will be described below with reference to the drawings.

First, an outline of the test mode entry according to the present invention will be described with reference to FIG. 1, and then a specific embodiment will be described with reference to FIG.

FIG. 1A is an explanatory diagram of a test mode entry according to the present invention.

Arrows in the figure mean transitions between modes. If the arrow passes through the bold line, it means that the transition must satisfy the condition indicated by the bold line. Also, the area surrounded by circles and ellipses in the figure is
One mode (normal mode, mode 1, etc.) is shown.

The left side of FIG. 1A shows the normal mode.

From this normal mode, as shown on the right side of the figure,
In order to make a transition (entry) to the vendor test mode, it is necessary to satisfy the conditions shown by the thick solid line.

That is, here, the super Vcc is applied to a predetermined specific pin, and the above-mentioned WCBR cycle is performed. At this time, depending on the data set (address key) given to the address pin, any one of the vendor test modes is selected. Specify whether to transit to the mode. That is, the address key is uniquely predetermined for each mode.

Now, once the vendor test mode is entered, the transition in the vendor test mode is the condition indicated by the thick dotted line (that is, "perform the WCBR cycle and specify the destination mode by the address key"). ) Can be done in. At this time, it should be noted that the application of the super Vcc is unnecessary.

When the vendor test mode is entered, the CBR (CAS before RAS refresh) cycle, the RAS only refresh cycle, or the test mode reset by entering a predetermined test mode (for example, in this example, , Vendor test mode mode 4 is the reset test mode), the vendor test mode is reset and the normal mode can be restored.

FIG. 1B shows the outline of another entry method. Here, the vendor test mode,
It is divided into two levels, the entry condition from the normal mode to the vendor test mode is the same as before, and the entry from the first level mode to the second level mode is WCBR.
This can be performed only by performing a cycle and designating an address key, and at this time, the operation of applying the super Vcc to the specific pin is unnecessary.

That is, the sub-base mode (existing in the first level mode), which is a mode capable of transitioning to a plurality of sub modes (existing in the second level mode), exists in the second level mode. The entry to the sub mode can be performed only by performing the WCBR cycle and designating the address key, and the operation of applying the super Vcc to the specific pin is unnecessary.

To return from the sub mode to the sub base mode, for example, give a specific address key and
A BR cycle may be carried out. To return from the sub-base mode to the normal mode, it is the same as in FIG.

FIG. 6 is a configuration diagram showing a specific circuit configuration for realizing the entry of FIG. 1 (b).

In this embodiment, a predetermined pin is
A super Vcc detection circuit 1 for detecting that the super Vcc is applied, a WCBR detection circuit 2 for detecting a WCBR cycle, and a logical product circuit 5 for taking a logical product of these two detection results. Decoding circuits 8 and 11 for decoding the value of the address key, a latch 9 for holding the first level vendor test mode state, and an output of this latch 9 are in the sub-base mode. A logical product circuit 10 for obtaining the logical product of the output 34 shown and the signal 26 showing the WCBR cycle, and a latch 1 for taking in the output 36 of the address key decoding circuit 11 according to the output 35 of the logical product circuit 10.
2 and are configured.

Each constituent element can be realized by an electronic device such as various logic gates, resistors and capacitors.

Further, a CBR (CAS before RAS) detection circuit 3 for detecting CBR, a RAS only detection circuit 4 for detecting a RAS only signal, an AND circuit 7 for obtaining a logical product of predetermined input signals, and a predetermined input. Although a logical sum circuit 6 for obtaining a logical sum of signals is also provided, these constituent elements are means for resetting the test mode held in the latch 9 and the latch 12, and the present invention Is not an essential component of.

Hereinafter, referring to the circuit of FIG. 6, FIG.
An operation for entering submode 1 (which exists in the second level mode) of the vendor test mode shown in FIG.

First, it is assumed that the latches 9 and 12 are reset in the initial state. In practice, these cycles were executed by performing a CBR cycle (FIG. 8A) and a RAS only refresh cycle (FIG. 9) after powering on the memory IC incorporating this circuit. This is performed by detecting such a situation and setting the circuit configuration such that the latch is reset.

First, in order to enter the first level sub-base mode, the super Vcc is applied to a predetermined specific pin (for example, the highest address pin).

As a result, the super Vcc detection circuit 1
Is a signal 25 indicating that the super Vcc is being applied.
Is output. Then, the WCBR cycle is executed by applying a predetermined signal to the WE (write enable) pin 22, the RAS pin 23, and the CAS pin 24 while applying the address key to the address pin of the memory IC. Here, WE (write enable) pin 22, R
The AS pin 23 and the CAS pin 24 are shown in FIG.
The predetermined signal is given so as to satisfy the signal relationship of (b). As a result, the WCBR cycle is executed.

Then, the WCBR detection circuit 2 outputs the WCBR
A signal 26 indicating the cycle is output.

At this time, the AND circuit 5 outputs the signal 29 indicating the WCBR cycle in which the super Vcc is applied.

At this time, the decoding circuit 8 decodes the value (address key) indicated by the plurality of address pins 21,
A signal is output to any one signal line of the signal lines 31 according to the value.

It is predetermined which signal line 31 the signal is to be output to, depending on the signal pattern input to the decoding circuit 8, and the decoding circuit 8 is set so that the determined input / output relationship is satisfied. Design and manufacture. The same applies to the configuration of the decoding circuit 11.

Now, the latch 9 captures the decode signal from the decode circuit 8 by using the signal 29 indicating the WCBR cycle to which the super Vcc output from the AND circuit 5 is applied as a trigger. Here, the value indicating the sub-base mode is applied as an address key to the address pin, so that the latch 9 outputs the signal 34 indicating the sub-base mode.

Once the sub-base mode is entered, it is not necessary to apply super Vcc to switch from this state to the sub-mode existing in the second level mode.

Subsequently, in order to enter the sub mode 1, the WCBR cycle is executed while applying a predetermined address key indicating the sub mode 1 to the address pin 21.

At this time, since the super Vcc is not applied, the super Vcc detection circuit 1 does not output the signal 25. The WCBR detection circuit 2 includes WE22, RAS23, C
The WCBR cycle is detected from the pattern of each operation of the AS 24, and the WCBR signal 26 is output.

Here, the AND circuit 5 receives the signal 26 but does not output the signal 29 because the signal 25 is not given.

On the other hand, since the signal 34 indicating the sub-base mode has already been input to the AND circuit 10, WC
Upon receiving the signal 26 from the BR detection circuit 2, a signal 35 indicating the WCBR cycle in the sub-base mode.
Is output.

The latch 12 receives the signal 36 output from the decoding circuit 11 by using the signal 35 as a trigger.
At this time, by applying a value indicating the sub-mode 1 to the address pin 21 as the address key, the signal indicating the sub-mode 1 is fetched in the latch 12 and the output 37 corresponding thereto is obtained. Similarly, entry to another submode 2 is performed by applying an address signal, which is an address key determined uniquely to the submode, to the address pin 21.

Although not shown, in order to execute a plurality of types of tests on the DRAM from outside the DRAM, the state inside the DRAM is set to a predetermined state which is predetermined according to the type of the test. It is sufficient to provide a test circuit for performing the test, and the test circuit generates the predetermined state according to the output of the latch 12. As an example, the test circuit has a function of applying a voltage of a predetermined value (a voltage that is not boosted) to a specific connection line of the connection lines connecting the plurality of memory cells. This function is activated by the output of latch 12.

Then, assuming that the predetermined state is that a voltage of a predetermined value is applied to the specific connection line, a memory test corresponding to the entered submode may be performed.

Although it has been stated above that the test mode reset circuit is not an essential constituent element of this embodiment,
The operation at the time of resetting the test mode will be briefly described below by taking the CBR (CAS before RAS) cycle as an example.

As one method of resetting the test mode, the WE (write enable) pin 22 of the memory IC,
A signal is applied to each of the RAS pin 23 and the CAS pin 24 so that the CBR cycle shown in FIG. 8A is executed, and the CBR cycle is executed.

As a result, the CBR detection circuit 3 is
The signal 27 is output. The OR circuit 6 uses the CBR signal 27
And the RAS only signal 28 and the output signal 33 of the AND circuit 7 are logically ORed and the signal 30 is output as a reset signal.

Therefore, the reset signal 30 is output by the input of the CBR signal 27. Receiving the reset signal 30, the latches 9 and 12 reset the output signals 32, 34 and 37, respectively.

In addition to this, in order to reset the test mode, the test mode may be reset by using a predetermined specific address key so as to instruct the reset of the test mode. .

In FIG. 6, a signal 31-1 which is one of the signals 31 output from the decoding circuit 8 is output.
Is a signal output from the decoding circuit 8 when an address key indicating a test mode reset is input. By executing the test mode entry cycle using the address key corresponding to this signal 31-1, a signal 29 indicating that the WCBR cycle is accompanied by application of the super Vcc is output, and the AND circuit 7 outputs the signal. 33 is output.

As a result, the OR signal 6 outputs the reset signal 30, the latches 9 and 12 are reset, and the test mode is released.

The super Vcc detection circuit 1, the WCBR detection circuit 2 and the C described above as the components of this embodiment have been described above.
The BR detection circuit 3, the RAS only detection circuit 4, etc., are respectively
It suffices to detect a specific state or a specific cycle to be detected and obtain an output corresponding to the specific state or cycle, and any specific circuit configuration may be used.

For example, the function required for the CBR detection circuit 3 is to output a CBR signal indicating this during the CBR (CAS before RAS) cycle, as shown in FIG. 8A.

Similarly, the function required of the WCBR detection circuit 2 is, as shown in FIG. 8B, a WCBR signal indicating this at the time of WCBR (CAS before RAS in a state where WE is activated) cycle. Is to be output.
Similarly, the function required of the RAS only detection circuit 4 is to output a RAS only signal indicating this during the RAS only refresh cycle, as shown in FIG.

The essence of the present invention does not depend on the specific circuit configuration of these individual components, but as an example, FIG. 10 shows a circuit configuration diagram of the WCBR detection circuit 2.

In FIG. 10, an AND gate 13 and a delay circuit 19-1 are circuits for detecting the falling edge of the CAS signal. Similarly, the AND gate 17 and the delay circuit 19-3 are circuits for detecting the falling edge of the RAS signal.

The operation of this circuit will be briefly described below with reference to FIGS. 11 and 10.

The falling edge of CAS detected by the AND gate 13 is delayed by the delay circuit 19-2 for a predetermined time and then applied to the AND gate 14.

Immediately after the fall of CAS, the AND gate 14 outputs a pulse indicating the fall of CAS delayed for a predetermined time only when RAS is at the high level.

FIG. 11 shows the output from the AND gate 14 (the output of the gate 14).

The gate 16 is an OR gate, and CAS
While the signal is at high level, the flip-flop 15
Then, the reset signal (R is a reset terminal) is continuously applied. The output of the gate 16 is shown in FIG.
Is as shown in. The flip-flop 15 is a set / reset type (RS type), and after the reset terminal is released, a pulse of a high-level signal is given to the set terminal (S is a reset terminal) to output the output (FIG. 11). , The output of the flip-flop 15) becomes a high level signal.

As shown in FIG. 11, after the reset signal from the gate 16 disappears at the fall of CAS, the flip-flop 15 is set so as to be output from the flip-flop 15 by the output pulse from the gate 14. To be done.

RAS falls after a lapse of a fixed time after the fall of CAS.

The AND gate 17 detects this falling edge, and through the delay circuit 19-4, the gate 16
Give a pulse to.

Since the OR gate 16 is a logical sum gate,
This pulse is applied to the reset terminal of the flip-flop 15 as it is, whereby the output of the flip-flop 15 is reset.

The gate 18 outputs a pulse obtained by delaying the falling signal of RAS by a predetermined time by the output of the flip-flop 15 only when the WE terminal is low, and WC
The BR signal 26 is output.

Although it has been described here that the AND gate 18 is opened only when the WE signal is at the low level, the CBR detection circuit 3 is configured so that the AND gate 18 is opened only when the WE signal is at the high level. is there.

FIG. 12 shows a configuration example of the super Vcc detection circuit 1. The principle of super Vcc detection is that the input voltage is divided by a voltage dividing circuit and judged from the divided voltage,
When a voltage equal to or higher than the super Vcc 20 is input, a signal indicating that the super Vcc is input is output to the signal line 25.

Therefore, the Schmitt trigger circuit detects whether or not the voltage equal to or higher than the divided voltage, which is output to the voltage dividing point when the voltage equal to or higher than the super Vcc is applied, is detected. The configuration is such that it is determined whether or not a voltage is input. Note that the voltage division may be performed by using a resistor as shown in the figure, or the voltage drop between the nodes of the transistor may be used.

Although the embodiment shown in FIG. 6 has been described above, the decoding circuit 8 and the decoding circuit 11 shown here are described.
Does not need to be clearly divided into two, it is one circuit,
It is possible to decode both signals in the first level mode and the second level mode. Further, in FIG. 6, the super Vcc and the WCBR cycle are detected separately and the logical product of them is taken, but the present invention is not limited to this, and as a result of performing the processing of individually detecting the signals, the super Vcc is obtained. Also, any circuit configuration may be used as long as it can be detected that the cycle is the WCBR cycle. What is important in this embodiment is that when the vendor test mode enters the sub mode, unlike the conventional case, the signal 3 indicating that the sub base mode is currently set instead of the super Vcc signal 25.
This is the point where 4 is used.

Although the embodiment based on the entry method shown in FIG. 1B has been described above, as another embodiment, FIG.
An embodiment based on the entry method shown in (a) is shown in FIG.

As can be seen with reference to FIG. 13, the individual components are identical to those already described in FIG. The same components are given the same reference numerals to facilitate understanding. It should be noted that duplicated description of the configuration of each component and the same operation description is avoided.

The present embodiment is largely different from the above-mentioned embodiments in that the output signal 32 of the latch 9 is input to the logical sum circuit 38 and the output signal of the logical sum circuit 38 is input to the logical sum circuit 39. The point is that the output signal of the logical sum circuit 38 is used in place of the super Vcc detection signal in order to perform the mode transition after once entering the vendor test mode. As a result, as long as a signal indicating any of the vendor test modes output from the latch 9 is generated as the input of the OR circuit 38, the super Vcc is specified for the transition to another test mode. The application operation to the pin becomes unnecessary.

In FIG. 13, it is assumed that the normal mode is set. That is, it is assumed that none of the signals 32 (mode 1, mode 2, mode 3, mode 4, mode 5) indicating that the test mode has been entered. Therefore, the signal 40 (super Vcc detection substitute signal) which is the output of the OR circuit 38 is not output. Therefore, in order to output the signal 41 from the OR circuit 39, it is necessary to apply the super Vcc to the predetermined specific pin.

Here, the super Vcc is applied to the specific pin to perform the WCBR cycle in which the address key is designated.
The super Vcc detection circuit 1 detects this and detects the super Vc.
The c detection signal 25 is output.

As a result, the OR circuit 39 causes the signal 41
Is output. On the other hand, the WCBR detection circuit 2 uses the WE signal 2
2, the RAS signal 23, and the CAS signal 24 are input, and when it is determined that these signals have a pattern as shown in FIG. 8B, it is detected that the WCBR cycle is set, and the WCBR detection signal 26 Is output. The logical product circuit 5 calculates the logical product of these two detection signals and outputs a signal 29.

The decoding circuit 8 decodes the address key applied to the address pin 21 and outputs one of the corresponding signals 31. Here, it is assumed that any one of the signals 31 other than the signal 31-1 instructing the test mode reset is output.

The address key applied to the address pin 21 and the test mode are uniquely associated with each other in advance. When the address key is input, the decoding circuit 8 responds to the corresponding test mode. The signal is output to the signal line.

As described above, also in this embodiment, the test signal (not shown) for starting with the output signal of the latch 9 as the starting signal may be provided.
As a result, various tests can be executed from the outside depending on the type of the signal 32.

The latch 9 sends the signal 31 to the signal 29.
Capture as a trigger and hold. This causes signal 3
Any one of the two is output and the test mode can be entered.

The OR circuit 38 takes the logical sum of the signals 32 and outputs a signal 40. The OR circuit 39 outputs the signal 40
The signal 41 is continuously output by the input of.

As a result, in order to apply the signal 29, which is the output of the AND circuit 5, to the latch 9 to switch the test mode, it is not necessary to apply the super Vcc, the WCBR cycle is executed, and only the address key is applied. With, you can switch the test mode. Even if the test mode is switched to another test mode, any one of the signals 32 indicating the signals from mode 1 to mode 5 is output,
By taking the logical sum of these in the logical sum circuit 38,
The output of signal 40 is maintained. Therefore, if one of the test modes is entered, switching between the test modes requires the super Vcc to the specific pin.
Need not be applied.

Although the configuration and operation of the embodiment of the present invention have been described above, it will be described with reference to FIG. 20 and FIG. 7 how an actual memory and test will be performed by utilizing this. To do.

FIG. 20 shows a configuration example of a DRAM to which the present invention is applied.

Test mode control circuit 4 in FIG.
7 is the same circuit as shown in FIG.

However, in FIG. 20, for convenience of explanation, the sub-base mode, the sub-mode 1 and the sub-mode 2 are three.
Mode is incorporated as a vendor test mode.

Therefore, the test mode control circuit 47 outputs the signal 48 indicating that the sub mode 1 is entered and the signal 49 indicating that the sub mode 2 is entered. Where submode 1
Is in a test mode that cancels the boosting of the word line drive voltage described earlier with reference to FIG. 19 and reduces the operation margin of the memory cell. A signal 48 indicating this is a peripheral circuit (word line drive) of the memory cell array. Voltage booster circuit)
It has been entered in. Then, when the signal of 48 is input, the booster circuit (41 in FIG. 19) cancels the boosting.

Sub-mode 2 shows the 4-bit parallel test function and is the test mode described above with reference to FIG. A signal 49 indicating this is input to the column address decoding circuit and the data input / output buffer.

FIG. 21 shows an example of the value of the address key required to enter each mode.

For example, in order to enter the sub-base mode, address pins 4 to 0 correspond to
The value "01101" may be given as the address key. As shown in FIG. 21, this sub-base mode has no influence on the operation of the memory except that it is in the vendor test mode.

FIG. 7 is a flow chart showing an example of a test procedure using these test modes.

First, in step 1, the sub-base mode is entered.

Here, it is necessary to apply the super Vcc to the specific pin, but it is necessary to apply the super Vcc to the specific pin only once in this test.

The sub-base mode is, as described above,
It has no effect on the operation as a memory. That is, in the sub-base mode, the parallel bit test is not performed, and the boosting of the word line drive voltage is not canceled.

Hereinafter, all the tests are performed under this sub-base mode.

The processing from step 2 to step 16 in FIG. 7 corresponds to the processing from step 1 to step 15 in FIG.

The only difference is that, in FIG. 7, in step 9, super Vcc is not applied to a specific pin.
This is the point where the mode is switched to sub mode 1. Therefore, here, the switching is completed within a time (120 (ns)) that is the time when the normal WCBR cycle is performed.

Actually, it takes some time to wait until the operation of the switched sub mode 1 becomes stable. However, compared with the switching time of 20 (ms) shown in FIG. It's a short time.

Therefore, compared with FIG. 3, the test time of FIG. 7 can be greatly shortened, and the test efficiency is improved.

In step 10 of FIG. 7, as a "special test", reading is performed with the boosted and canceled word line drive voltage, and it is tested whether or not reading can be performed without an operating margin.

Now, in step 11, a transition is made to the sub-base mode, and in step 12, a read test with a normal operation margin is performed. Then, in step 13, the address of interest is updated, and the processes from step 8 to step 14 are repeated until the test for the maximum address is completed. As described above, in this test, the test modes are frequently switched, but in steps 9 and 11, it is not necessary to apply the super Vcc to a specific pin, so the test modes can be switched in an extremely short time. You can

Although FIG. 7 described above is a test flowchart corresponding to FIG. 1B, a test flowchart corresponding to FIG. 1A is shown in FIG.

Here, "mode 1" corresponds to the above-mentioned "sub-base mode", and except that it is one of the test modes, if the boosting is not canceled, the parallel bit This is a test mode in which no test is performed, that is, no substantial test is performed.

Mode 2 corresponds to submode 1 described above and is a test mode for canceling the boosting of the word line drive voltage.

In FIG. 16, in step 1, mode 1 is entered from normal mode. At this time, it is necessary to apply the super Vcc to the specific pin, but when switching between the modes in Step 9 and Step 11, the application of the super Vcc is not necessary, and the test mode can be switched in an extremely short time. Therefore, the time for the test itself is significantly shortened.

The processing in other steps is as shown in FIG.
Since there is no difference from the processing shown in, the explanation is avoided here.

As described above, according to the present invention, the super V
cc is applied to a specific pin to perform a WCBR cycle to enter the vendor test mode from the normal mode. Therefore, the user's erroneous entry prevention function is maintained as in the conventional method, and the vendor test mode is temporarily entered. After that, it is not necessary to apply the super Vcc to a specific pin for switching between the test modes.
As a result, by utilizing this for the switching of the test mode, which frequently occurs during the test, the mode switching can be performed only by the time required for the WCBR cycle.

Therefore, the memory I using the vendor test mode is maintained while maintaining the conventional erroneous entry prevention function.
It is possible to significantly reduce the C test time.

[0192]

As described above, it is possible to provide a semiconductor device having an erroneous entry prevention function and capable of switching a plurality of test modes in a short time.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a test mode entry according to the present invention.

FIG. 2 is an explanatory diagram of a conventional test mode entry.

FIG. 3 is a flowchart showing a test procedure of a memory IC using a test mode.

FIG. 4 is an explanatory diagram of a process of performing a test mode entry during a test with a tester.

FIG. 5 is an explanatory diagram of a time required for test mode entry.

FIG. 6 is a configuration diagram of an embodiment according to the present invention.

FIG. 7 is a flowchart showing a memory IC test procedure according to the present invention.

FIG. 8 is an explanatory diagram of a CBR cycle and a WCBR cycle.

FIG. 9 is an explanatory diagram of a RAS only refresh cycle.

FIG. 10 is a configuration diagram of a WCBR cycle detection circuit.

FIG. 11 is an explanatory diagram of the operation of the WCBR cycle detection circuit.

FIG. 12 is a configuration diagram of a super Vcc detection circuit.

FIG. 13 is a configuration diagram of another embodiment according to the present invention.

FIG. 14 is a configuration diagram of a tester.

FIG. 15 is an explanatory diagram of a parallel bit test function.

FIG. 16 is a flowchart showing a test flow using an embodiment according to the present invention.

FIG. 17 is a configuration diagram of a DRAM.

FIG. 18 is an explanatory diagram of an operation cycle of DRAM.

FIG. 19 is a configuration diagram around a memory cell array of a DRAM.

FIG. 20 is a block diagram of a DRAM according to the present invention.

FIG. 21 is an explanatory diagram of an address key.

[Explanation of symbols]

1 ... Super Vcc detection circuit, 2 ... WCBR detection circuit, 3
... CBR detection circuit, 4 ... RAS only detection circuit, 5 ... AND circuit, 6 ... OR circuit, 7 ... AND circuit, 8 ... Decode circuit, 9 ... Latch, 10 ... AND circuit, 11 ... Decode circuit, 12 ... Latch, 25 ... Super Vcc signal, 2
6 ... WCBR signal, 27 ... CBR signal, 34 ... Sub-base mode signal

Continuation of front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical display location G11C 11/401 G11C 11/34 371 A (72) Inventor and companion Naoto 5-20, Kamimizumotocho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Business Division No. 1

Claims (4)

[Claims] 1. In a dynamic random access memory (DRAM) in which memory cells are arranged in a matrix, a plurality of address pins for receiving a signal for specifying a memory address, a plurality of data pins for receiving and writing data to and from the DRAM, and a data In order to enable writing to the memory, the write enable (WE) pin that receives the first digital signal and the signal applied to the address pin are used to specify the row direction position of the memory cells arranged in a matrix. A row address strobe (RAS) pin that accepts a second digital signal and a column of memory cells arranged in a matrix to enable the signal applied to the address pin to be read as a signal to be read. You can read it as a signal that specifies the direction position. Column address strobe (Colu
(mn Adress strobe (CAS) pin), and a test circuit that sets the internal state of the DRAM to a predetermined state that is predetermined according to the type of test in order to execute multiple types of tests on the DRAM from outside the DRAM. When the first predetermined condition is satisfied, among a plurality of test modes existing, a test mode preliminarily associated with the pattern of the signal applied to the address pin is entered, and the test mode is associated with the test mode. When the test circuit is started to enable the execution of the test on the DRAM from outside the DRAM, the first predetermined condition is once satisfied, and the second predetermined condition is further satisfied. , The test mode that is previously associated with the pattern of the signal applied to the address pin from the currently entered test mode. And a test mode circuit for activating the test circuit to enable execution of a new test from outside the DRAM associated with the test mode, the test mode circuit comprising: A case where the second digital signal is applied to the RAS pin after the third digital signal is applied to the CAS pin in a state where the first digital signal is applied to the pin, It is determined that the first predetermined condition is satisfied when a voltage (super Vcc voltage) of a predetermined value or more is applied to a pin specified in advance among the address pin and the data pin. Then, a first entry unit for entering a test mode according to the pattern of the signal given to the address pin and the first digital unit for the WE pin. If the second digital signal is applied to the RAS pin after the third digital signal is applied to the CAS pin in the state that the second digital signal is applied to the CAS pin, the second predetermined condition is satisfied. A dynamic random access memory having a test function, characterized in that it has a second entry portion for judging that the test pattern has been entered and for entering a test mode according to a pattern of a signal given to an address pin. 2. The test circuit according to claim 1, further comprising an applied voltage circuit that applies a voltage of a predetermined value to a specific connection line of the connection lines that connect a plurality of memory cells, and the predetermined state. And a dynamic random access memory having a test function in which a voltage having a predetermined value is applied to the specific connection line. 3. The first, second, and third digital signals are low-level digital signals, and the super Vcc voltage is higher than a power supply voltage of DRAM. A dynamic random access memory having a test function. 4. In a dynamic random access memory (DRAM) in which memory cells are arranged in a matrix, a plurality of address pins for receiving a signal for specifying a memory address, a plurality of data pins for receiving and writing data to and from the DRAM, and a data In order to enable writing to the memory, the write enable (WE) pin that receives the first digital signal and the signal applied to the address pin are used to specify the row direction position of the memory cells arranged in a matrix. A row address strobe (RA) for receiving a second predetermined digital signal for enabling the reading as a signal
A third predetermined digital signal for allowing the signals given to the S) pin and the address pin to be read as a signal designating the position of the memory cells arranged in a matrix in the column direction is accepted. Column address strobe (CAS) pin and in order to execute multiple types of tests on the DRAM from outside the DRAM, the internal state of the DRAM is set to a predetermined state that is predetermined according to the type of test. And a first predetermined condition is satisfied, a sub-base mode, which is a mode including a plurality of test modes, is entered, and further, a second predetermined condition is satisfied,
One of the test modes that constitutes the sub-base mode, the test mode that is associated in advance with the pattern of the signal applied to the address pin is entered, and the test mode from outside the DRAM that is associated with the test mode is entered. A test mode circuit that activates the test circuit that enables execution of a test on a DRAM, the test mode circuit including the WE pin and the first digital signal applied to the CAS pin. A case in which the second digital signal is applied to the RAS pin after the third digital signal is applied, and the pin is one of the address pin and the data pin and is specified in advance. , A voltage higher than a predetermined value (super Vcc voltage) is applied, and the pattern of the signal applied to the address pin is further Signal matches the signal pattern given to a predetermined address pin, it is determined that the first predetermined condition is satisfied, and the first entry section for entering the sub-base mode and the WE pin When the second digital signal is applied to the RAS pin after the third digital signal is applied to the CAS pin while the digital signal of 1 is applied, the second predetermined condition is satisfied. A dynamic random access memory having a test function, which comprises a second entry section that determines that the above condition is satisfied and enters a test mode according to the pattern of the signal applied to the address pin.