JPH11238400A - Semiconductor integrated circuit device, device and method for testing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having an inexpensive and efficient self-test function for a built-in memory. SOLUTION: This semiconductor integrated circuit device 10 tests a defective bit of an incorporated memory 14 by an incorporated memory test circuit 12 is accordance with control from a general purpose tester 100. The incorporated memory test circuit 12 writes data having the prescribed value for an address corresponding to an external memory 16 whenever a defective bit in the incorporated memory 14 is detected. The general purpose tester 100 analyzes a defective address of the incorporated memory 14 based on data mapped in the external memory 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a self-test function for a built-in memory, a test device therefor and a test method therefor.

[0002]

2. Description of the Related Art FIG. 9 is a schematic block diagram showing a configuration of a test system 2000 for a conventional memory device 1110 having a built-in memory test function.

A memory device 1110 with a built-in memory test function is equipped with a BIST circuit (not shown) for performing a built-in self test (BIST) for a built-in memory.

A memory device 1110 having a built-in memory test function is mounted on a test jig 1100, and an external clock signal ext. CLK,
A control signal Sc for controlling the operation of the memory device 1110 is supplied.

For example, from a general-purpose tester 100, a BIS
When a control signal instructing to start the T operation is provided, the memory device 1110 outputs the external clock signal ex.
t. While operating in synchronization with CLK, test data is written to the built-in memory mounted therein, and then the data read from the built-in memory is compared with an expected value for the test result to determine whether the built-in memory is good or not. To the general-purpose tester 100.

By performing such a test, the operation to be performed by an external general-purpose tester that tests memory device 1110 is determined by generating signal Sc instructing memory device 1110 to start a built-in self-test. And external clock signal ext. It is only necessary to finally determine the quality of the chip based on the supply of CLK and the quality / failure determination information output from the chip after a predetermined time.

[0007] That is, there is a feature that the load on the general-purpose tester 100 is greatly reduced.

[0008]

However, the configuration of the conventional test system 2000 as described above has the following problems.

That is, first, the information output from the memory device 1110 is the pass / fail judgment information FS for the built-in self-test, so that only this information is used to analyze the distribution of defective addresses existing in the built-in memory, for example. hand,
It is difficult to perform a defective address analysis operation such as estimating a process in which the defective address was generated.

Furthermore, if the information output from the memory device 1110 is only the pass / fail judgment information FS, it is difficult to perform a redundancy analysis for replacing a bit corresponding to a defective address in the internal memory with a redundant bit. It is.

In addition, even when the defective address of the memory built in the memory device 1110 is transferred to the outside, the memory device 1 with the built-in memory test function can be used.
In order to analyze defective address information and perform redundancy analysis on the memory device 110, it is necessary to create a test program dedicated to the memory device 1110.

Moreover, generally, the test speed of the built-in memory of the memory device 1110 having the built-in memory test function is as follows.
Since the operation speed is higher than that of a general-purpose tester, there is a problem that it is difficult to perform the test operation itself or to perform a test operation with a sufficient operation margin depending on the general-purpose tester.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a memory device having a built-in self-test function by using a general-purpose memory test device. It is an object of the present invention to provide a semiconductor integrated circuit device, a test device, and a test method capable of performing a defective address analysis and a repair analysis efficiently at low cost.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor memory device including an internal data storage unit, wherein the internal data storage unit includes a plurality of memory cells arranged in a matrix each holding data. Data input / output control means for transmitting and receiving storage data between a memory cell array and a memory cell selected in accordance with an internal address signal; and a control signal and an external clock signal from outside the semiconductor integrated circuit device. Corresponding to the result of writing and reading of predetermined data to and from a corresponding memory cell while sequentially changing an internal address. hand,
It determines whether the memory cell is good or defective, and outputs an internal address signal and a write control signal to the storage device to a storage device external to the semiconductor integrated circuit device according to the determination result.

According to a second aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, the internal test control means includes: a control logic signal generating means for controlling an operation test of the internal storage means; Test pattern storage means for holding a data pattern, timing generation means for generating an internal clock for controlling the timing of an operation test, and determination data corresponding to a comparison result between data read from the internal storage means and an expected value And external storage control means for controlling an operation of writing the internal address signal and the determination data to the storage device according to the determination data.

According to a third aspect of the present invention, there is provided a test apparatus comprising: a signal receiving means for receiving an external control signal and an external clock signal; a semiconductor integrated circuit device to be tested for receiving a signal from the signal receiving means; Controlled,
A storage device for holding data from the semiconductor integrated circuit device, wherein the semiconductor integrated circuit device includes internal data storage means, and the internal data storage means includes a plurality of memories arranged in a matrix each holding data. Data input / output control means for transmitting and receiving storage data between a memory cell array including cells and a memory cell selected in accordance with an internal address signal; a control signal from a signal receiving means and an external clock signal Further includes an internal test control means for performing an operation test of the internal storage means, wherein the internal test control means sequentially changes the internal address and writes the result of writing and reading of predetermined data to a corresponding memory cell. In response, the memory cell is determined to be good or defective, and an internal address signal and a write control signal to the storage device are sent to the storage device in accordance with the determination result. To output.

According to a fourth aspect of the present invention, there is provided a test method of a semiconductor integrated circuit device having a built-in self-test function for a built-in internal memory, wherein data in a predetermined address area of an external storage device is stored in a first value. , Setting the semiconductor integrated circuit device to start a built-in self test, and causing the semiconductor integrated circuit device to perform a built-in self test to determine whether a bit in the internal memory is good or defective. Rewriting the data at the corresponding address of the external storage device to a second value different from the first value according to the result; analyzing the data held in the external storage device; Analyzing the distribution of.

[0018]

FIG. 1 is a schematic block diagram showing a configuration of a memory test system 1000 according to an embodiment of the present invention.

The memory test system 1000 includes a general-purpose tester 100, a test jig 200 for mounting a device to be tested by the general-purpose tester, and a general-purpose tester 10.
0 to the test jig 200 for the external clock signal ex
t. A data bus 18 for providing the CLK and the control signal Sc, a control signal Scr to the test jig 200, an address signal Add, and a data bus 20 for transmitting input / output data Di are included.

The test jig 200 further receives an external clock signal ext. An input terminal 22 that receives the CLK and the control signal Sc, a semiconductor integrated circuit device 10 that is a device under test that receives a signal from the input terminal 22 and has a built-in memory self-test function, and an output from the semiconductor integrated circuit device 10 A control signal Scw;
The data bus 20 transfers data between the external memory 16 that receives and stores the address signal Add and the write data Di and stores the data Di in the corresponding address, and the input / output terminal 28 of the external memory 16. Input / output terminal 30 for
And

The semiconductor integrated circuit device 10 has an input / output terminal 2
2 from the external clock signal ext. An input / output terminal 24 for receiving a CLK and a control signal Sc; a built-in memory test circuit 12 for controlling a self-test operation in accordance with a signal from the input / output terminal 24; a built-in memory 14 having a predetermined storage capacity; It includes a control signal Scw output from the test circuit, an address signal Add, and an input / output terminal 26 for outputting write data Di.

The control signal Sc output from the general-purpose tester 100 instructs the semiconductor integrated circuit device 10 to start the built-in self-test of the built-in memory.
00 supplied from the external clock signal ext. The built-in self-test of the built-in memory 14 is performed in synchronization with CLK. The result of the built-in self test of the write memory 14 is such that predetermined write data Di is stored in an address corresponding to the address of the internal memory 14 of the external memory 16 controlled by the control signal Scw output from the internal memory test circuit 12. By being written, it is stored in the external memory 16.

The data stored in the external memory 16 is transmitted from the external memory 16 to the general-purpose tester 10 in accordance with the control signal Scr and the address signal Add from the general-purpose tester 100.
The data Di is read into the general-purpose tester 100 for 0.

FIG. 2 is a schematic block diagram for explaining in more detail the configuration of the semiconductor integrated circuit device 10 having the built-in self test function of the built-in memory shown in FIG.

The built-in memory test circuit 12 receives an external clock signal ext. CLK and control signal Sc, built-in memory test controller 122 controlling write and read operations of test data in built-in memory 14, and data read from built-in memory and expected written in built-in memory. A data determination unit 132 for comparing with a value, an address signal Add corresponding to the internal address for which the data determination has been performed, and a plurality of determination results for a plurality of data signals output from the data determination unit and read at a time Information signals FQ1 to FQn and a plurality of data signals Di (= D
1 to Dn), the write control signal, the address signal, and the write data signal are sent to the external memory 16 in response to the pass / fail determination information FS indicating whether the read data matches the expected value. External memory controller 13 that outputs
4 is included.

The built-in memory test controller 122 includes:
External clock signal ext. A test control logic circuit for receiving a clock signal CLK and a control signal Sc, and controlling a test operation of the built-in memory;
, And a memory test pattern storage register 128 for outputting the held memory test pattern, and a test control logic circuit 124 for controlling the internal clock signal int. Timing generator 12 that outputs CLK
6, the memory test pattern and the internal clock signal i
nt. A signal for testing the internal memory according to CLK,
That is, it includes a built-in memory test signal generator 130 that outputs a control signal SCw, an address signal Add, and a write data signal Di to the built-in memory. After writing data to internal memory 14, internal memory test signal generator 130 controls internal memory 14 to read a data signal corresponding to the written test pattern, and controls data determination unit 132. The data determining section 132 is caused to perform a comparison operation between the expected value given and the read data signal Di.

The built-in memory 14 has a control circuit 142 for controlling a write or read operation of the built-in memory 14 in accordance with a control signal Scw and an address signal Add, and memory cells for holding data arranged in a matrix. A row selection circuit 144 controlled by the memory cell array 148 and the control circuit 142 to select a corresponding row in the memory cell array.
And a column selection circuit 146 controlled by the control circuit 142 to select from a corresponding column of the memory cell array and perform a data read operation, and output data read from the column selection circuit 146 to the outside, or And an input / output circuit 150 for applying the applied data to column selecting circuit 146.

Memory cell array 148 includes a redundant memory cell column (not shown) for replacing a memory cell column including a defective bit.

FIG. 3 shows the test control logic circuit 124.
Receives the control signal Sc instructing the start of the built-in memory test from the outside, and starts the operation of the timing generator 126 and the operation of reading the pattern from the memory pattern storage register. The built-in memory test signal generator 130 receives the input timing signal int. Various signals for testing the built-in memory are generated based on the CLK and the test pattern data.

For example, when the internal memory is a dynamic random access memory (hereinafter, DRAM), a row address strobe signal R is used as an operation control signal.
AS, a signal equivalent to the column address strobe signal CAS, and the like. If the built-in memory 14 is a static random access memory (hereinafter, SRAM), a signal equivalent to the chip select signal CS, etc.
Generated according to the interface specifications.

FIG. 3 is a timing chart for explaining an operation of writing test data to built-in memory 14 in semiconductor integrated circuit device 10 shown in FIG.

That is, FIG. 3 shows a transition of signals from when an internal memory test start signal is externally generated to when data is written to internal memory 14.

Referring to FIG. 3, when a built-in memory test start signal is generated from general-purpose tester 100 at time t1, built-in memory controller 122 responds to this at time t2 from timing generator 126 to internal clock. The signal int. Start output of CLK.

Further, the built-in memory test controller 1
Reference numeral 22 outputs a reset signal to the built-in memory at time t3 after a predetermined time has elapsed. Built-in memory is
In response to this reset signal, internal registers and operation modes are set to predetermined states.

At a time t4 after a predetermined time has elapsed, the built-in memory test controller 122 sends a control signal Scw and an address to the built-in memory 14 based on the pattern data registered in the memory test pattern storage register 128. Outputs signal A0, data signal D0, etc., and writes data to the built-in memory. Further, at time t7, an address signal A1 having an updated address is output, and data D1 is written to internal memory 14.

FIG. 4 is a block diagram showing the data judgment unit 132 shown in FIG.
FIG. 3 is a schematic block diagram for describing the configuration of an external memory controller 134 in more detail.

Data determination section 132 is activated in response to a strobe signal output from built-in memory test signal generator 130, receives data D1 to Dn simultaneously read from built-in memory 14, and outputs data D1 to Dn. Comparator 1322 that outputs a result of comparison with corresponding expected values EV1 to EVn output from signal generator 130
1326 and logic gate 13 which receives outputs from comparators 1322-1326 and outputs pass / fail determination information FS
28.

That is, the comparator 1322 outputs “H” level data when the corresponding read data Di matches the expected value EVi (i = 1 to n), and outputs “L” when it does not match. Output level data respectively.

Logic gate 1328 includes comparators 1322-
If any one of the output signals from 1326 is at “L” level, it becomes “H” level.
The determination information FS is output.

The external memory controller 134 has an address latch 1342 for receiving and holding an address signal Add given when reading data from the internal memory 14;
Data latches 1344 that receive data determination information FQ1 to FQn output from comparators 1322 to 1326, respectively, and a signal that controls write operation of data to an external memory by receiving pass / fail determination information FS. , And an external memory interface 1348 for writing data.

The data latch 1344 and the address latch 1342 are controlled by the pass / fail judgment information FS.
Only when signal FS attains an active state ("H" level), the corresponding data holding operation is performed.

The external memory data write control signal generator 1346 controls the interface 1348 with the external memory in response to the activation of the signal FS, and outputs a write control signal for the external memory and an external memory. Data determination information FQ1-FQ as write data signals for
Qn and the address signal Add held in the address latch 1342 are output as an address signal to an external memory.

That is, when the built-in memory controller 122 enters a data read cycle of the built-in memory 14 during the built-in self-test period, the data judgment section 132 compares the data read from the built-in memory 14 with the built-in memory. A comparison operation with an expected value output from the test controller 122 is performed. External memory controller 134
Performs an operation of transferring the read address and the read data information to the external memory when a negative determination is made as a result of the data determination.

FIG. 5 is a timing chart for explaining the operation of the read cycle in the built-in self-test of the memory test controller 122, the data determination unit 132, and the external memory controller 134 shown in FIGS.

At time t0, built-in memory test controller 122 outputs, to built-in memory 14, a built-in memory operation control signal instructing an internal read operation and an address signal designating address A0 for performing the read operation.

In response, read data R from internal memory 14 are read from time t1 to time t2.
0 is output. Here, it is assumed that the read data R0 is a general term for the data D1 to Dn output from the internal memory 14 at one time.

On the other hand, the built-in memory test controller 12
2, the internal memory test signal generator 130 outputs the time t1
During the period from time t2 to comparators 1322 to 132
6, the expected value data E0 is output.
Here, it is assumed that the expected value data E0 is a general term for the expected value data EV1 to EVn output corresponding to each of the data D1 to Dn read at a time.

At a predetermined time during the period from time t2 to time t3, an active strobe signal is output from built-in memory test signal generator 130. In response, comparators 1322 to 1326 perform a comparison operation between the expected value and the read data, and as a result, signals FQ1 to FQn are output from the comparators.

In the example shown in FIG. 5, the read data output from data lines 1 and 2 do not match the expected value data, and comparator 1322 and comparator 1324
Output data FQ1 and FQ2 outputted from
Level, and the other comparator outputs FQ3 to FQn
Are all at “H” level.

In response to signal FQ1 and signal FQ2 being at "L" level, pass / fail determination information FS output from logic gate 1328 changes to "H" level.

In response, address latch 1342 holds address signal A0, and data latch 134
4 holds data determination information FQ1 to FQn, respectively.

As will be described later, this data latch 1
344 and the data held in the address latch 1342 are transmitted to the external memory data write control signal generator 1346.
And is output to the external memory 16.

Subsequently, at time t7, the built-in memory test signal generator 130 again sends the built-in memory operation control signal for instructing the read operation to the built-in memory 14 and the address corresponding to the updated address address A1. And output signals.

At a predetermined time from time t8 to time t9, read data R1 is output from built-in memory 14, and built-in memory test signal generator 130 sends expected value signal E1 to data determination unit 132. Each is output.

At a predetermined time in the period from time t9 to time t10, an active strobe signal is output from built-in memory test signal generator 140, and comparators 1322 to 1326 output signals FQ1 to FQ1. FQ
n are output.

In the example shown in FIG. 5, at time t9
From the time t10 to the time t10 are all at “H” level. In other words, it is assumed that the read data R1 and the expected value data E1 match for all data.

At this time, the pass / fail judgment information FS output from logic gate 1328 is at "L" level.

Therefore, neither the address latch nor the data latch is activated.

FIG. 6 shows the external memory controller 13 during the read cycle of the built-in self test shown in FIG.
4 is a timing chart showing a time change of a signal output to an external memory from FIG.

In the period from time t2 to time t3, in accordance with the control of external memory data write control signal generating section 1346, the external memory interface 1348 sends the external memory 16 , A write control signal for controlling the write operation is output.

On the other hand, the address signal A0 corresponding to the defective bit held in the address latch 1342 is output to the external memory 16.

At this time, the data determination information FQ1 to FQn held in the data latch 1344 are also output from the external memory interface 1348 to the external memory 16.

That is, the data judgment information is written into the external memory 16 with respect to the address corresponding to the address where the defective address of the internal memory 14 exists.

On the other hand, during the period from time t9 to time t10, the internal memory test signal generator 130
At the time when the active strobe signal is output, the pass / fail judgment information FS is in an inactive state (“L” level).
From the external memory controller 134, the external memory 16
In contrast, neither a write control signal instructing a write operation nor a write address signal to an external memory is output.

Therefore, the addresses for which no defect was found in the built-in self test are stored in the external memory 1
No writing of data determination information is performed for No. 6.

As described above, a general-purpose SRAM or a non-volatile memory as the external memory 16 does not need to perform a data recovery operation, so that it is necessary to hold the result of the built-in self test. Are suitable. Further, the controller 134 of these external memories is a general-purpose SRA.
The configuration may be the same as that of the memory controller used for the M and the general-purpose nonvolatile memory, and it is easy to design the memory controller.

The external memory interface 13
48 has a built-in timing generator (not shown) therein, and is based on logic information output from an address latch 1342, a data latch 1344 and an external memory data write control signal generator 1346 in the external memory controller 134. , Generate a signal of a level that can be received directly by the external memory.

As described above, the external memory 16
This is for storing defective address information of the internal memory 14, and has a configuration in which defective information for each corresponding I / O of the internal memory 14 is stored at the same address as the defective address of the internal memory 14.

Therefore, the capacity of the external memory and the I / O
The number of O's is preferably equal to or greater than that of the internal memory 14.

When the capacity of the external memory 16 and the number of I / Os are smaller than those of the built-in memory 14, the address and I / O are degenerated at the time of the built-in memory test, so that the failure information can be collected and stored. is there.

For example, in built-in memory 14, the operation of replacing the redundant memory cell column with the normal memory cell column is performed by setting the number of columns corresponding to the number of bits (I / O numbers) to be read at a time as one block. If block replacement is performed, the rescue operation of the built-in memory 14 to the redundant memory can be performed as it is even if the address and I / O are degenerated.

FIG. 7 shows a semiconductor integrated circuit device 10 as an example.
FIG. 2 is a conceptual diagram showing a configuration in a case where an external memory SRAM having the same number of I / Os and a similar capacity as a built-in memory and a general-purpose memory tester 100 are connected to a device 10 having a built-in memory self-test function. .

FIG. 7 shows a case where built-in memory 14 has a capacity of, for example, 64 bits and the number of data I / Os (the number of data ports) is four. Therefore, a general-purpose SRAM having the same capacity and the same I / O count of 4 bits is used as the SRAM 16. Memory device chip select signal, write control signal WE and address signals A0-A5, data output terminals I / O0-I
/ O3 is connected to the corresponding input / output pin of the SRAM 16, respectively.

On the other hand, each pin of the external memory 16 is further connected to a test terminal of a general-purpose tester.

That is, the control signal of the general-purpose memory tester 100 is connected to input / output pins such as a chip select signal and a write control signal of the external memory 16, and the address signal of the general-purpose memory tester 100 is connected to the address pin of the external memory 16. And the data read / write terminals of the general-purpose memory tester 100 are connected to the data input / output terminals I / O0 to I / O3 of the external memory 16, respectively.

FIG. 8 shows the test system 10 shown in FIG.
10 is a flowchart for explaining the operation of the 00.

When the test on the semiconductor integrated circuit device 10 by the general-purpose tester 100 is started (step S10)
0) First, a reset operation of the data held in the external memory 16 is performed (step S102).

That is, as described later, when the bit data corresponding to a certain address in the internal memory 14 is determined to be defective, a logical value opposite to the logical value of the data written to the internal memory is set to All addresses in the external memory are written in advance by a general-purpose tester. Subsequently, the general-purpose tester 100 outputs a control signal instructing the semiconductor integrated circuit device 10 to start a built-in memory test (step S104).

At this point, the general-purpose tester and the external storage device are electrically disconnected temporarily (step S106).

Subsequently, built-in memory test circuit 12 in semiconductor integrated circuit device 10 generates an internal address for testing the built-in memory and writes the internal test data to built-in memory 14 (step S108).

Subsequently, built-in memory test circuit 12 reads data from built-in memory 14 and performs a comparison operation with an expected value (step S110).

Subsequently, built-in memory test circuit 12 determines whether or not a defective bit exists in the read address (step 112).

When there is a defective bit (step S1)
12), the built-in memory test circuit 12
And outputs a defective address, write data (data determination information) and a write control signal (step S118).
The process returns to step S110.

On the other hand, when the built-in memory test circuit 12 determines that there is no defective bit (step S11)
2) Subsequently, the built-in memory test circuit determines whether or not the built-in memory test has been completed (step S11).
4). If the internal memory test has not been completed, the process returns to step S110.

On the other hand, when the built-in memory test is completed, the general-purpose tester 100 responds accordingly.
By analyzing the data held in the memory 6, the information of the defective address in the internal memory 14 is extracted,
A redundant circuit analysis and a defective address analysis for the built-in memory 14 are performed.

Thus, the test operation is completed (step S
120). In the external memory 16, data having a logic value opposite to the data to be written when it is determined in advance that a defective bit exists in the internal memory 14, and
The external memory controller 134 of the semiconductor integrated circuit device 10 having the memory self-test function does not write data to the external memory 16 unless it is determined that a defective bit exists. Therefore, only the data in the external memory 16 at the address where the defective bit exists has an inverted value.

That is, when the built-in memory test is completed, a defective address of the built-in memory 14 is mapped in the external memory 16.

With such a configuration, the defective address information in the built-in memory 14 can be indirectly read by the general-purpose tester 100 by using a read operation on the external memory 16 composed of a general-purpose memory. Is possible.

That is, the general-purpose tester 100 performs the operation of reading data from the general-purpose memory.
This can be performed by using a conventional memory test pattern or program, and the reading speed can be ensured with a sufficient margin irrespective of the test speed of the built-in memory 14.

Therefore, it is possible to transfer data accurately and in accordance with the speed of taking in the defective address memory or the like mounted on the tester and the speed of the repair analysis device, without waste.

Therefore, it is possible to realize an inexpensive and efficient analysis using the existing test means for the failure address analysis and the repair analysis of the internal memory 14.

[0092]

According to the present invention, the result of the operation test of the internal data storage means is written by the internal test control means to the corresponding address of the external storage device. Therefore, in the test of the semiconductor integrated circuit device, it is possible to use a test device corresponding to the test specification of the external storage device, and it is possible to perform an inexpensive and efficient test.

According to a second aspect of the present invention, in the test of the semiconductor integrated circuit device having the built-in self-test function, the result of performing the operation test of the internal data storage means by the internal test control means is stored in the test apparatus. Since it is possible to write to the corresponding address of the device, it is possible to use an external test device corresponding to the test specification of the storage device, and it is possible to perform an inexpensive and efficient test.

According to the test method of the third aspect, the test result of the internal memory in the semiconductor integrated circuit device can be mapped in the external storage device by rewriting data at a corresponding address of the external storage device. It is possible. Therefore, a test of the semiconductor integrated circuit device can be performed at an operation speed or the like conforming to the read and write specifications of the external storage device, and a low-cost and efficient failure address analysis and a repair analysis can be performed. It is.

[Brief description of the drawings]

FIG. 1 shows a test system 100 according to an embodiment of the present invention.
FIG. 3 is a schematic block diagram illustrating a configuration of a zero.

FIG. 2 is a schematic block diagram for explaining a configuration of a semiconductor integrated circuit device 10 having a built-in memory test function shown in FIG.

FIG. 3 is a timing chart for explaining a write operation in a built-in memory test operation of the semiconductor integrated circuit device 10;

FIG. 4 is a data determination unit 13 of the semiconductor integrated circuit device 10;
FIG. 2 is a schematic block diagram for describing a configuration of a second memory controller and an external memory controller;

FIG. 5 is a timing chart for describing a read operation during a built-in memory self-test of the semiconductor integrated circuit device 10;

FIG. 6 is a timing chart for explaining a write operation to the external memory 16 during a built-in memory self-test period of the semiconductor integrated circuit device 10;

FIG. 7 is a schematic block diagram when the test system 1000 shown in FIG. 1 is configured as a general-purpose memory SRAM.

FIG. 8 is a flowchart showing a processing flow of a test method of the present invention.

FIG. 9 is a schematic block diagram showing a configuration of a conventional test system 2000.

[Explanation of symbols]

10 built-in memory semiconductor integrated circuit device with self-test function, 12 built-in memory test circuit, 14 built-in memory,
16 external memory, 18, 20 data bus, 22, 2
4, 26, 28, 30 data input / output terminals, 100 general-purpose tester, 122 built-in memory test controller, 1
24 test control logic circuit, 126 timing generator, 128 memory test pattern storage register, 13
0 built-in memory test signal generator, 132 data determination unit, 134 external memory controller, 142 control circuit, 144 row selection circuit, 146 column selection circuit, 148
Memory cell array, 150 data input / output circuit, 200
Test jig, 1000, 2000 test system.

Claims (4)

[Claims] 1. A semiconductor integrated circuit device, comprising: an internal data storage means, wherein the internal data storage means includes: a memory cell array including a plurality of memory cells arranged in a matrix each holding data; Data input / output control means for transmitting and receiving storage data to and from a memory cell selected in accordance with an address signal, wherein the data input / output control means includes a control signal and an external clock signal from outside the semiconductor integrated circuit device. An internal test control unit for performing an operation test of the internal storage unit, wherein the internal test control unit sequentially changes the internal address and responds to a result of writing and reading of predetermined data to and from the corresponding memory cell. And determining whether the memory cell is good or bad, and performing a determination on a storage device external to the semiconductor integrated circuit device according to the determination result. Outputting section address signal and a write control signal to the storage device, a semiconductor integrated circuit device. 2. The internal test control unit includes: a control logic signal generating unit that controls an operation test of the internal storage unit; a test pattern storage unit that holds a pattern of the predetermined data; and a timing of the operation test. Timing generating means for generating an internal clock for performing the operation; determining means for outputting determination data corresponding to a comparison result between the read data from the internal storage means and an expected value; and the storage device according to the determination data. 2. The semiconductor integrated circuit device according to claim 1, further comprising: an external storage control unit that controls an operation of writing an internal address signal and the determination data to the internal memory. 3. A signal receiving means for receiving an external control signal and an external clock signal; a semiconductor integrated circuit device to be tested for receiving a signal from the signal receiving means; A storage device for holding data from the semiconductor integrated circuit device, wherein the semiconductor integrated circuit device includes internal data storage means, wherein the internal data storage means includes And a data input / output control unit for transmitting and receiving storage data between a memory cell array including memory cells of the type described above and a memory cell selected in accordance with an internal address signal. An internal test control unit for performing an operation test of the internal storage unit in response to an external clock signal; The stage determines pass / fail of the memory cell according to a result of writing and reading of predetermined data to and from the corresponding memory cell while sequentially changing the internal address. A test device that outputs the internal address signal and a write control signal to the storage device to the storage device. 4. A test method for a semiconductor integrated circuit device having a built-in self-test function for a built-in internal memory, comprising: setting data in a predetermined address area of an external storage device to a first value; Instructing the semiconductor integrated circuit device to start the built-in self-test; and causing the semiconductor integrated circuit device to perform the built-in self-test, and determining whether a bit in the internal memory is good or bad. Accordingly, rewriting the data at the corresponding address of the external storage device to a second value different from the first value, analyzing the data held in the external storage device, Analyzing the distribution of defective bits.