JPS6155758A - Microcomputer applied bus tester - Google Patents

Abstract

PURPOSE:To discover easily and rapidly a faulty place of respective peripheral circuits of a microcomputer applied device by replacing CPU of a microcomputer application device where a fault occurs with the titled device. CONSTITUTION:When a personal computer 30, where a fault occurs, is tested, a microprocessor 31 of the computer 30 is replaced with a bus tester 20, and a prescribed clock signal is inputted from an external clock generating circuit 32 to the device 20. Thus, the clock signal inputted in the device 20 is suitably frequency-divided, and a Q clock signal, etc., necessary to an action timing of respective peripheral circuits (memory 33 and I/O port 34, etc., excluding CPU) of the computer 30, are generated. The signal is frequency-divided in the device 30, outputted through a counter circuit and repeatedly circulated while an address signal is successively changed. Thus, a faulty place of respective peripheral circuits of a microcomputer applied device can be discovered easily and rapidly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a microcomputer application device, for example, a bus test device for a personal computer. By performing a predetermined test in place of the above, it is possible to easily trace and investigate defective locations on each bus of the application device.

2. Description of the Related Art Conventionally, in order to trace the defective parts of this type of micro-combinatorial equipment, methods such as tracing the signal waveforms of various parts using an oscilloscope have been used. A signal generator is required for each application device, and if the CPU stops operating (for example, if the hold signal is left open), the circuit itself will not operate. There was a problem that testing was difficult.〇Problems to be solved by the invention The present invention was made in order to solve the above problems.
For defective microcomputer application equipment,
By simply replacing (for example, replacing) the CPU of that device, it can be used to test all microcombiator application devices that use the same type of CPU, and all transmissions from the microprocessor based on the clock signal input are required. By forcibly generating various signals, and at the same time, circulating the address signals regularly, it is possible to easily and quickly find faulty parts in each peripheral circuit (excluding the CPU') of the micro combinator application device. According to the present invention, by inputting a clock signal,
A signal generating circuit is provided for generating all the necessary address signals, data signals, and various control signals to be sent from the microprocessor, and the signal generating circuit sequentially counts up the number of counts based on the input of the clock signal. A counter circuit is provided which repeatedly generates an address signal t- from its output side. A bus test device for a microcomputer application device is provided. In the test device of the present invention, the count number of a counter circuit provided in the test device is sequentially counted up by seven based on the input of a clock signal, and the output side of the test device is Address signal from? By sequentially and repeatedly generating the faults, it is possible to easily trace the entire sequence of defective locations in the circuit parts connected to each address bus. Furthermore, in the test device, in addition to generating the address signal, all necessary control signals (e.g., read/write control signal, Q clock signal, enable signal, etc.) are sent from the microprocessor.
When the convolution control signal is generated, the required data signal is written.Also, even if the switch for switching read or write is set to the read side, the data signal is always written only once after reset. By performing the write operation (that is, initializing the data bus), it is possible to reliably test the circuit parts connected to each data bus, including the memory.

Note that a signature analyzer, for example, is used to operate the bus test device of the present invention and identify defective locations on each bus. In other words, using the signature analyzer, the signal (
In reality, changes in the signal that occur repeatedly within a certain period of time)
Signature value (a numerical value compressed to, for example, 16 bits using the variation function of the signal, which has a different value depending on the situation of the sequence of the signal variation) t
- By checking and comparing the signature value with the signature value during normal operation, it is possible to trace the defective location on the bus. In addition, it is also possible to trace defective locations using a measuring instrument such as a synchronoscope. Embodiment FIG. 1 shows the overall configuration of a bus test device as an embodiment of the present invention. In the figure, Ao to A1 are on the left side.
．． (for address signal), and 5TART/5TOP
Bin terminals (for start/stop) are shown,
Also on the right side are RESET (for resetting) and MRDY (
(for memory ready), Q (for Q clock), E (for enable clock), EX (for external clock input), Do~to, (for data signal), R/W (for input/read signal), Vcc (for core source) and GND (for grounding) are shown.The arrangement of the bin terminals shown in the figure is the same as that of the 6809 CPU, and the However, by adapting the arrangement of the bin terminals to the arrangement of other CPUs, it can of course be used as a testing apparatus for devices using other CPUs.

Next, in the figure, reference numeral 1 denotes a counter circuit for dividing the frequency of an external clock signal input from an external peripheral circuit, that is, a circuit under test, to its CLK terminal via a bin terminal EX and an inverter 71, 72. In this embodiment, a clock signal whose frequency is divided by two is output from the output terminal QA, and a clock signal whose frequency is divided by four is output from the output terminal Q.

Reference numeral 2 denotes a latch circuit, to which an external clock signal from the bin terminal EX via the inverter 71 is inputted to its CLK terminal, and to its data input terminal 2D, the clock signal divided by four is input from the output terminal Q11 of the counter circuit 1. As a result, the 4-divided clock signal is output from the output terminal 2Q as it is for the Q clock signal, and the Q clock signal generated inside the test equipment is output as is. A signal is supplied to the external circuit via the bin terminal 1f as a clock signal for its operation.

゛The Q clock signal output from the terminal 2Q is then input to the input terminal 3D, and the clock signal input to the terminal 3D is input to the external clock signal (4 of the Q clock signal) input to the CLK terminal. The signal is outputted from the output terminal 3Q as an enable signal with a deviation of one clock [corresponding to one cycle of the Q clock signal] of the frequency tM (double the frequency tM). That is, the enable signal is a clock signal that is 901 times out of phase with the Q clock, and is supplied to the external circuit together with the Q clock signal through the enable signal μ pin terminal El. The clock signal outputted from the output terminal Q (the clock signal obtained by dividing the frequency of the external clock signal by 2) and the clock signal outputted from the output terminal Q (the clock signal obtained by dividing the frequency of the external clock signal by 4) are the OR circuit 61. and from the output side of the OR circuit 61, the L level of the clock signal whose frequency is divided by two appears every other time (that is, the interval at which the clock signal changes from the H level to the L level is divided by the frequency by two). This signal is input to the data input terminal ID of the latch circuit 2 via the inverter 73. As a result, a signal obtained by inverting the signal input to the terminal ID is output from the output terminal IQ, and the inverted signal and the terminal MRD
The mesori ready signal input from Y is the OR circuit 6.
2 and is input to the terminal ET of the counter circuit. As a result, when the CPU is using the path and the memory ready signal is input, the counting operation of the counter circuit is stopped and the clock is prevented from advancing.

Therefore, when the operation of peripheral circuits cannot keep up with the clock, the clock can be delayed.

Note that the reset signal inputted from the bin terminal RESET is inputted to the clear terminal of the counter circuits 31, 32, 33.34 and the latch circuit 4, which will be described later, through the inverter 74.75t-.

Now, as described above, the output terminal Q of the counter circuit 1
The 4-divided clock signal outputted from B is first processed by a counter circuit (in the illustrated embodiment, configured for 16-bit output by four 4-bit binary counters 31, 32, 33, and 34). Therefore, the counter circuit sequentially counts up the count number according to the input clock signal, and connects to the output side of the nfC address signal pin terminal 80 from AlB. Address signals 2ro, o are output.

0.0'' to rF, F, F, F(16)J, while repeatedly changing the cycle.

Then, the count value of the counter circuit overflows and rF,F
, F, F (16)'' to rO, O, O, OJ, each time the terminal RC (
A clock signal is supplied from the overflow terminal) to the terminal ICK of the latch circuit 4. When this clock signal is input, a signal is output from the output terminal IQ of the latch circuit 4 according to the open/closed state of the switch 8 at the time of input. The switch 8, which outputs a signal, is turned off when reading data from the external circuit (memory) each time depending on the purpose of the test, and ta is turned off when data is written to the external circuit (memory). Depending on the open/closed state of the switch 8, a read or write control signal is sent from the output terminal IQ of the latch circuit 4 to the external circuit via the bin terminal R/W'. Clear terminal IC of latch circuit 4
A reset signal (a signal for initializing the device when the power is turned on) is input from the bin terminal RESET to LR, and even when the switch 8 is set to the read side (off), the signal is output only once after the reset. is the output terminal IQ
The write signal is configured to be sent as the t-L level.0 This is the micro combinator's memo IJCRA
Since the state of M) is undefined when the power is turned on, it is necessary to set the memory contents to a specific state the first time the reset signal is input (if this is not done, the waveform of the node mentioned above 0 and 5 is a tri-state buffer circuit,
Each of the manual terminals IAI to IA4 and 2A1 to 2A
Each opening/closing part of the switch 9 is connected to 4.

On the other hand, the respective output terminals IYI to IY4 and 2Y1 to 2Y4 are connected to data signal pin terminals, and the read or write control signal is input to the terminals IG and 2G. As a result, during writing (that is, when the signals input to terminals IG and 2G are at the L level), the data set by each opening/closing section of the switch 9 is transmitted to each pin terminal D0 to t- is output to the external circuit via the terminal IG.
and when the signal input to 2G is at H level),
The buffer circuit 5 is placed in a high impedance state and output of the data signal is blocked.

FIG. 2 shows, as another embodiment of the present invention, the structure of a bus test device for replacing a CPU of the type in which the Q clock signal and enable clock signal are input from an external clock generation circuit. Only the parts that are different from the embodiment are shown.

In the figure, 11 is a multiplexer whose input terminal IAI
The Cti and Q clock signals are input through the inverter 151, and the output side of the inverter 151 is further input to the exclusive OR gate (14). An enable clock signal whose phase is shifted by 90 degrees from the Q clock signal is also input to the exclusive OR gate 14 through an inverter 152. As a result, on the output side of the exclusive OR gate 14, a clock signal with twice the frequency of the clock signal on the long side is generated, and! ! *A double frequency clock signal is input to the other input terminal IB of the multiplexer 11.

Reference numeral 12 denotes a latch circuit, and an enable clock signal is inputted to the clock terminal CLK of each inverter 152'i, and a switch 13 is connected to its data input terminal. As a result, from the output terminal Q, an H level or an L level is output depending on the open/closed state of the switch 13.
A signal is supplied to the input terminal S of the multiplexer 11, thereby selecting the n clock signal input to the input terminal IA or IB and outputting it from the output terminal IY. The signal is supplied to the counter circuit in the same manner as in the case shown in the figure.

Note that the operating speed of the counter circuit, etc. can be changed by selecting the clock signal input to the input terminal IA or IB.

As shown in FIG. 3, when testing nine personal comviators, for example, when a defect occurs, using the trench bottom t'L north pass testing device, a personal computer 300 microprocessor is installed as shown in FIG. Replace the bus test equipment 20 incorporating the test circuit as shown in Figures 31'i and i1 (for example, insert each bin terminal of the bus test equipment WL20 onto the microprocessor 31t-extracted board), and A predetermined clock signal is input from the clock generation circuit 32 to the test apparatus.

As a result, in the embodiment shown in FIG. W11, the input clock signal is appropriately frequency-divided within the test equipment (in the embodiment shown in FIG. 1, the frequency is divided by 4), and Each peripheral circuit (Mesori 33, Bottle 34,
Q required for operation timing of CRT control circuit 35, etc.)
Generates a clock signal and an enable clock signal. In the embodiment shown in FIG. 2, the Q clock signal and the enable clock signal are inputted from an external clock generation circuit, and this type of CPU can be replaced.

Next, the clock signal input as described above or the clock signal obtained by appropriately frequency-dividing the clock signal in this test device is supplied to a counter circuit provided in this test device, and thereby the counter circuit is sequentially divided. The address signal outputted from the output side of the counter circuit is changed from rO, 0, O, OJ to rB', F, F, F.
(16) Repeat and circulate sequentially up to J.

Furthermore, a read or write control signal is generated depending on the setting state of the switch in each circulation cycle, and a predetermined data signal is written during write control. Note that even if the switch is set to the read side, data signals are written only at the time of reset.

As described above, the bus test device according to the present invention generates all address signals sequentially in accordance with the input of an external clock signal, and also sends out each necessary control signal from the microprocessor. Since it has a built-in function to output data signals, the CPU' of the defective microcomputer application device is
By replacing gt with this test equipment of the same model as U and performing the prescribed test (for example, by checking the fern nature value at each node on each bus using the fern nature analyzer mentioned above), it is easy to locate defective parts. (CP of the applied equipment
UL--in the remaining peripheral circuits) can be tracked.

Effects of the Invention According to the present invention, it is possible to easily and quickly conduct a sub-inspection to trace the failure location (excluding the CPUr) of a microconvenience application device in which the specific failure location is unknown. A bus test bag (if
k can get 0

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the overall configuration of a bus test device for a microcomputer application device as an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a bus test device as another embodiment of the present invention. Only different components? The circuit diagram shown in FIG. 3 is a diagram illustrating the usage state of the bus test device of the present invention. (Explanation of symbols) 1... Counter circuit (branch circuit), 2...
...Latch circuit, 31.32, 33.34...
Counter circuit %4...Latch circuit, 5...
...Tri-state buffer 7 circuits, 11...Multiplexer, 12...Latch circuit, 2o...
...Bus test equipment, 30...Microcomputer application equipment (Bernal computer).

Claims (1)

[Claims] 1. A signal generation circuit is provided that generates address signals, data signals, and various control signals that need to be sent out from the microprocessor in response to input of a clock signal, and the signal generation circuit is equipped with 1. A bus test device for a microcomputer application device, comprising a counter circuit that sequentially increments a count based on an input and repeatedly generates an address signal from its output side.