JPH01250771A - Analyzing device for operation of logic circuit - Google Patents

Abstract

PURPOSE:To reduce the number of processes and to shorten a time required for design and verification of a logic circuit, by stipulating an operation mode by a time series of a combinational logic of state and control signals. CONSTITUTION:A model (a) of a logic circuit, coded data (b), test data (c), an expected value (d) and the definition (e) of an operation mode are inputted in an input processing 1, and a coding processing 2 and an operation mode analyzing processing 3 are executed on the basis of the model of the logic circuit and the coded data. A circuit prepared by an operation mode analyzing circuit combining processing 4 on the basis of the result of the above operation mode analysis is added to the model of the logic circuit. Next, code simulation 5 is conducted, using the model of the logic circuit and the test data as inputs. In this simulation, an operation mode is determined from the history of a value of a signal being monitored. In the case when said mode can not be determined or when the expected value and the operation mode are not matched with each other, an operation monitoring processing 6 of the logic circuit operates, and tracing outputs of the operation mode and of the name of a bug candidate signal and a signal are executed. In this way, the analysis of the operation of the logic circuit is executed.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a method for analyzing the operation of a large-scale and complex logic circuit, and in particular, when debugging a logic circuit, the operation is analyzed by simulation. This invention relates to a method for analyzing the behavior of logic circuits that allows for easy tracking and, if a bug is included, to find a candidate for it.

(Conventional Technique #) Conventionally, large-scale, complex logic circuits have been debugged by understanding their operation using state transition diagrams and the like. However, with this method, the operating mode of the circuit must be understood as a time series of states, and the time series of states to express the operation of a complex circuit is long.
It took some time to understand how it worked. In addition, if a bug is included, it is necessary to trace the signal values in the reverse direction (input side) one by one in order to find the cause of the abnormal operation. (Problem to be solved by the invention) The present invention As mentioned above, it is necessary to reduce the time required to understand the operation of large-scale and complex logic circuits, and to identify bugs in the logic circuit model and test data that are causing abnormal operation. The purpose is to shorten the time required.

[Structure of the invention]

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention defines operation modes by a temporal sequence of combinatorial logic of states and control signals, and organizes them along the time axis. By doing so, during simulation, you can dynamically determine the signals to be monitored while referring to this information, and narrow down the operation mode. The method is to analyze the Further, in the present invention, the operation of the logic circuit is clarified by using a method of symbolizing the value of the data signal and performing symbol similation.

(Function) The present invention is the technical means described above. By defining the operating mode and tracking the operating mode by monitoring accordingly during simulation, and by symbolizing data signals, it is possible to easily understand the logic circuit during simulation. The operation can be displayed clearly at a glance. In addition, in the present invention, bugs in the logic circuit model and test data can be easily discovered by inferring the behavior of the logic circuit model at the time of Simini Lane 91, the definition of the operation mode, and the operation mode given as the expected value. becomes possible.

(Example) The present invention will be explained in detail based on examples.

FIG. 1 shows a diagram showing the processing and data flow in an embodiment of the present invention. In Figure 1, input processing l
Input the logic circuit model a, the encoded data b, the test data C, the expected value d (including the operation mode), and the constant gear e of the operation mode, and create a logic circuit model using the logic circuit model and the encoded data. The symbolization process 2 assigns symbol values to the data signals in the data signal, and the operation mode analysis process 3 organizes the fixed values of the operation modes in the time axis direction. The circuit created by the operation mode analysis circuit synthesis process that synthesizes the circuit for detection is added to the logic circuit model that has been subjected to the symbolization process, and then the logic circuit model that includes the model of the circuit for operation mode analysis is added. Symbolic simulation 5 is performed using the test data as input. In this case, the operation mode is determined from the history of the values of the input signals being monitored, and if the operation mode cannot be determined or the expected value does not match the operation mode, the cause of the abnormal operation is determined. Logic circuit operation monitoring processing 6 operates to infer bug candidates for the logic circuit model, and the operation of the logic circuit is monitored by tracing the operation mode and outputting the name of the bug candidate signal and the trace of the signal. Perform the analysis.

Next, the fixed limit of the operation mode will be explained using a very simple example. FIG. 2 shows an example of a constant gear operation mode, and FIG. 3 is a timing chart thereof. In FIG. 2, f is the data write mode g, and h is the data read mode. Clock signal C in all three modes
At time n1 after the rising time of LK, the control signal 0-Q signal falls, and at the same time in the read mode (g, h), the control signal RD falls. Furthermore, in mode h, it is determined that the control signal BRD falls at a time n2 after the falling of the Ion and Q signals. Also, the expected value is tl in f mode.
The write data is applied to the data signal 11iDATA two clocks after tl, and in the h mode, the read data is applied to the data signal line DATA one clock after tl. However, in h mode, only 1 byte of data is carried on the DATA signal. The falling edge of the l0RQ signal was detected at time n1 after the rising edge of the CLK signal by monitoring the CLK, l0RQ, and RD multiplied signals during simulation using the above operating modes organized in the time axis direction through operating mode analysis processing. At this stage, the operating modes are narrowed down to f and gth h, and if the RD double signal monitoring value also shows a fall at the same time, the operating modes are narrowed down to g and h. Using the operation modes organized in the time axis direction in this way, you can track the operation modes and identify the signals and signals that caused the deviation, starting from the last remaining operation mode candidate. The operation of the logic circuit is analyzed by retaining the reason and outputting it as a candidate for the bug that caused the malfunction of the logic circuit.

〔Effect of the invention〕

By employing the method of the present invention to understand the operation of a logic circuit when designing and verifying the logic circuit, the number of man-hours can be reduced and the time required for designing and verifying the logic circuit can be shortened. In particular, in debugging logic circuit models and test data, the use of the present invention to locate design errors reduces debugging time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing processing and data flow in one embodiment of the present invention. FIG. 2 is a diagram showing an example of a constant timing of the operation mode, and FIG. 3 is a timing diagram of the operation mode shown in FIG. 2. 1... Input processing, 2... Symbolization processing, 3... Operating mode analysis processing, 4... Operating mode analysis circuit synthesis processing, 5... Simulation 1 6... Operation monitoring processing 1 a *bt 't dt e...Input data, fl
g, h...operation mode. 0, M c L:L e
Figure l

Claims (7)

[Claims] (1) Using means for inputting a logic circuit model and test data, and means for specifying an operation mode, a simulation is performed using the input logic circuit model and test data, and at that time, the logic circuit is a model of the logic circuit and the mode of operation to identify the mode of operation;
A logic circuit behavior analysis method characterized by dynamically changing the signals to be monitored during simulation based on the history of the monitored signal values and automatically tracking the behavior while determining the operation mode. 2. The method for analyzing the operation of a logic circuit according to claim 1, wherein the operation mode of the logic circuit is specified by a time series of a combinational logic equation based on a state signal and a control signal. (3) The logic according to claim 1, characterized in that a model modularized according to a hierarchy based on functions is used as a model of the logic circuit, and correspondingly, the operation mode is specified hierarchically. Circuit behavior analysis method. (4) As a logic circuit model, the input signals of each hierarchically designed module are divided into data signals and control signals, and the values of the data signals are symbolized in the simulation, and the data signal values are 2. The method for analyzing the operation of a logic circuit according to claim 1, wherein the operation of the logic circuit is analyzed by displaying a correspondence between a symbol value at a point of change in the signal value and an actual signal value. (5) The logic circuit according to claim 1, characterized in that an operation mode is given as an expected value, and a comparison is made with an operation mode specified during simulation to obtain a signal name of a mismatched portion, and its expected value and signal value. Motion analysis method. (6) The operation of the logic circuit is analyzed by automatically inferring candidates that cause abnormal operation of bugs in the logic circuit model and test data from the operation mode. A method for analyzing the operation of a logic circuit according to any one of the following. (7) A claim characterized in that the operation of the logic circuit is analyzed by automatically generating a circuit that determines a specified operation mode during simulation, adding it to a logic circuit model, and performing simulation. 1. Operation analysis method of the logic circuit described in 1.