JPS62204171A - Monitored aging method for integrated circuit - Google Patents

Abstract

PURPOSE:To expel defective elements by holding an integrated circuit in a standby state for a specified period in a monitored aging process. CONSTITUTION:A signal generating part 2 for generating the signal to be supplied to the integrated circuit 3 to be tested, a discriminating part 4 for taking in the output signal from the circuit 3 and discriminating whether the circuit is defective or non-defective and a timer 5 for setting time are provided to the integrated circuit. A logic '1' is generated from the timer 5 during the time t0-t1, t2-t3 and a logic '0' is generated therefrom during the time t1-t2. A signal such as normal clock is thereby applied to the circuit 3 via an AND gate A from the generating part 2 during the time t0-t1, t2-t3. The output signal from the circuit 3 is fed via an AND gate B to the discriminating part 4, by which the ordinary monitored aging is executed. On the other hand, the logical level of the output from the timer is the '0' and the gates A, B are held closed during the time t1-t2 and therefore, the signal such as clock is no longer supplied to the circuit 3 and the circuit 3 is held in the standby state. The defective element is expelled in the above-mentioned manner.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for monitored aging of integrated circuits.
In particular, the present invention relates to a monitored aging method suitable for screening integrated circuits whose defects can be detected by placing them in a standby state during aging.

[Background of the invention]

In conventional monitored aging equipment, integrated circuit devices are kept in an operating state continuously during the aging process, so the defective phenomenon shown in Figure 1 occurs even though power is supplied to the integrated circuit. There is a drawback in that it is not possible to eliminate integrated circuits that cause defective phenomena by turning them off to a standby state.

Furthermore, as this type of testing device, the
Although the number is publicly known, no consideration was given to the test time, etc.

[Purpose of the invention]

An object of the present invention is to provide a monitored aging method capable of eliminating integrated circuits exhibiting the above-mentioned defective phenomena.

[Summary of the invention]

The defective phenomenon targeted by the present invention occurs when the integrated circuit is placed in a standby state, as shown in FIG.

Focusing on this, defective elements are eliminated by leaving the integrated circuit in a standby state for a certain period of time during the monitored aging process.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. A signal generating section 2 for generating a signal to be supplied to an integrated circuit under test (hereinafter referred to as FDUT) 3, a determining section 4 for determining whether the output signal of the DUT 3 is good or bad, and time setting. The timer 5 for this is the essential component for realizing this discovery. From timer 5, time to
Logic 1111 is generated between ~t1 and t2~t3,
The period from time t1 to t2 generates logic '0''. By doing this, t o -t + and t2 to t
Time 3 is from DUT3 to DUT through AND gate A.
A signal such as a regular tarokku is added to DUT5.
The output signal is sent to the determining section 4 through AND gate B and processed, so that normal monitored aging is performed. On the other hand, since the logic level of the output of timer 5 is 10' during the period from t1 to t2, the AND
Since gates A and B are closed, signals such as clocks are no longer supplied to DUT3.
It goes into standby mode.

What was described in Fig. 2 is the explanation about the DUT 3 which enters the standby state by stopping the supply of input signals such as clock signals. Some can be put into standby by changing the logic level. An example in this case is shown in FIG.

In this case as well, t1 in FIG. 1 is similar to the explanation in FIG.
~t2 timer 5 generates a logic level to put the DUTs in standby mode.

By performing the above-described monitored aging, it is possible to detect DUTs 3 whose characteristics deteriorate during the standby state from t1 to t2 by determining them in the operating state from t2, thereby making it possible to eliminate defective DUTs.

Note that the timer 5 shown in FIGS. 2 and 3 may be a timer configured by a crystal oscillation circuit and a kakuntal logic circuit.

〔Effect of the invention〕

According to the present invention, it is possible to eliminate DUTs exhibiting a defective phenomenon whose characteristics are deteriorated only in a normal standby state, but which recover once when put into an operating state.

[Brief explanation of drawings]

Fig. 1 is a graph showing the operating mode and changes over time in the characteristics of a defective integrated circuit targeted by the present invention, Figs. 2 and 3 are two examples of the present invention, and Fig. 2 is a graph showing the DUT input. When the DUT enters standby state due to stoppage of signal supply,
FIG. 3 shows an embodiment in which the DUT is provided with a standby terminal or a power down terminal. 1...AND gate, 2...signal generation section, 3...DUT. 4... Judgment unit, 5... Timer. 1st circle to also l t2
3 hours 2 concave

Claims (1)

[Claims] A monitored aging method for integrated circuits, characterized in that the integrated circuit is placed in a power-down (standby) state for a certain period of time or more during the aging process.