JPS5779536A - Signal distributing circuit - Google Patents

Signal distributing circuit

Info

Publication number
JPS5779536A
JPS5779536A JP55153534A JP15353480A JPS5779536A JP S5779536 A JPS5779536 A JP S5779536A JP 55153534 A JP55153534 A JP 55153534A JP 15353480 A JP15353480 A JP 15353480A JP S5779536 A JPS5779536 A JP S5779536A
Authority
JP
Japan
Prior art keywords
signal lines
circuit
signal
terminating
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55153534A
Other languages
Japanese (ja)
Inventor
Hideki Nishimori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55153534A priority Critical patent/JPS5779536A/en
Publication of JPS5779536A publication Critical patent/JPS5779536A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To obtain the same effect with the equivalent equalization of signal line length at the input terminal of a receiving circuit, by supplying differential inputs to a driving circuit which generates a complementary clock, a terminating circuit for reflection prevention, and the receiving circuit. CONSTITUTION:When three receving circuits are provided, the lengths of signal lines 12 and 13 are so determined that l1=l1' and l2=l2', where the line lengths between positive inputs of registers 20 and 21, and 21 and 22 are l1 and l2, and those between negative inputs of the registers 21 and 20, and 22 and 21 are l1' and l2'm. Then, a driving circuit 10 outputs a positive and a negative complementary clock signal, having a constant-gradient leading or trailing edge, to signal lines 12 and 13 by an input from a clock signal input line 11. A terminating circuit 30 has a resistance value equal to the characteristic impedance values of the signal lines 12 and 13 and terminates the signal lines 12 and 13 at a terminating voltage source VT.
JP55153534A 1980-10-31 1980-10-31 Signal distributing circuit Pending JPS5779536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55153534A JPS5779536A (en) 1980-10-31 1980-10-31 Signal distributing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55153534A JPS5779536A (en) 1980-10-31 1980-10-31 Signal distributing circuit

Publications (1)

Publication Number Publication Date
JPS5779536A true JPS5779536A (en) 1982-05-18

Family

ID=15564614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55153534A Pending JPS5779536A (en) 1980-10-31 1980-10-31 Signal distributing circuit

Country Status (1)

Country Link
JP (1) JPS5779536A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57182819A (en) * 1981-05-08 1982-11-10 Toshiba Corp Synchronous clock controlling circuit
JPH05233093A (en) * 1992-02-21 1993-09-10 Nec Corp Circuit and method for supplying clock signal
FR2783944A1 (en) * 1998-09-28 2000-03-31 Nec Corp Signal distribution circuit and method of connection to a signal line
WO2005081004A1 (en) * 2004-02-19 2005-09-01 Advantest Corporation Skew adjusting method, skew adjusting device, and test instrument
KR100989577B1 (en) 2008-03-12 2010-10-25 주식회사 유니테스트 Module under test board
US10363381B2 (en) 2013-01-31 2019-07-30 Smiths Medical International Limited Medical infusion fluid heat exchange apparatus and warming systems

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57182819A (en) * 1981-05-08 1982-11-10 Toshiba Corp Synchronous clock controlling circuit
JPH05233093A (en) * 1992-02-21 1993-09-10 Nec Corp Circuit and method for supplying clock signal
FR2783944A1 (en) * 1998-09-28 2000-03-31 Nec Corp Signal distribution circuit and method of connection to a signal line
US6323716B1 (en) 1998-09-28 2001-11-27 Nec Corporation Signal distributing circuit and signal line connecting method
WO2005081004A1 (en) * 2004-02-19 2005-09-01 Advantest Corporation Skew adjusting method, skew adjusting device, and test instrument
KR100832172B1 (en) 2004-02-19 2008-05-23 주식회사 아도반테스토 Skew adjusting method, skew adjusting device, and test instrument
US7397289B2 (en) 2004-02-19 2008-07-08 Advantest Corporation Skew adjusting method, skew adjusting apparatus, and test apparatus
KR100989577B1 (en) 2008-03-12 2010-10-25 주식회사 유니테스트 Module under test board
US10363381B2 (en) 2013-01-31 2019-07-30 Smiths Medical International Limited Medical infusion fluid heat exchange apparatus and warming systems

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