JPS57182819A - Synchronous clock controlling circuit - Google Patents
Synchronous clock controlling circuitInfo
- Publication number
- JPS57182819A JPS57182819A JP56068160A JP6816081A JPS57182819A JP S57182819 A JPS57182819 A JP S57182819A JP 56068160 A JP56068160 A JP 56068160A JP 6816081 A JP6816081 A JP 6816081A JP S57182819 A JPS57182819 A JP S57182819A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- clocks
- wiring
- modules
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Electric Clocks (AREA)
Abstract
PURPOSE:To satisfy always the set-up time and the hold time of circuit elements, by supplying clocks having a prescribed phase difference to each of plural modules and selecting clocks properly. CONSTITUTION:A clock 12 is transmitted from a CPU, which is not shown in a figure, to plural modules l-n (n=3 in the figure) through a gate 4 and a wiring 5. The clock 12 is inputted as clocks 13-15 from gates 6-8. A return part 5 of the wiring 5 is connected to gates 11-9 in order, and the clock 12 is inputted as clocks 18-16. Two kinds of clock having the same period and a phase shift are supplied to each of modules 1-3. The phase shift is adjusted by the pattern length of the wiring 5. Thus, two kinds of clock are used selectively to satisfy the set-up time and the hold time of each circuit elements in case of the transfer between respective modules.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56068160A JPS57182819A (en) | 1981-05-08 | 1981-05-08 | Synchronous clock controlling circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56068160A JPS57182819A (en) | 1981-05-08 | 1981-05-08 | Synchronous clock controlling circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57182819A true JPS57182819A (en) | 1982-11-10 |
Family
ID=13365722
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56068160A Pending JPS57182819A (en) | 1981-05-08 | 1981-05-08 | Synchronous clock controlling circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57182819A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5184027A (en) * | 1987-03-20 | 1993-02-02 | Hitachi, Ltd. | Clock signal supply system |
JPH07121261A (en) * | 1993-10-21 | 1995-05-12 | Nec Corp | Clock distribution circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5779536A (en) * | 1980-10-31 | 1982-05-18 | Nec Corp | Signal distributing circuit |
-
1981
- 1981-05-08 JP JP56068160A patent/JPS57182819A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5779536A (en) * | 1980-10-31 | 1982-05-18 | Nec Corp | Signal distributing circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5184027A (en) * | 1987-03-20 | 1993-02-02 | Hitachi, Ltd. | Clock signal supply system |
JPH07121261A (en) * | 1993-10-21 | 1995-05-12 | Nec Corp | Clock distribution circuit |
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