JPS56152357A - Offset potential applying method - Google Patents

Offset potential applying method

Info

Publication number
JPS56152357A
JPS56152357A JP5508380A JP5508380A JPS56152357A JP S56152357 A JPS56152357 A JP S56152357A JP 5508380 A JP5508380 A JP 5508380A JP 5508380 A JP5508380 A JP 5508380A JP S56152357 A JPS56152357 A JP S56152357A
Authority
JP
Japan
Prior art keywords
circuit
differential input
potential
resistance
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5508380A
Other languages
Japanese (ja)
Inventor
Masahiro Fuwa
Toyoji Yasuda
Tadashi Takei
Sumio Yoshida
Shinichiro Obara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP5508380A priority Critical patent/JPS56152357A/en
Publication of JPS56152357A publication Critical patent/JPS56152357A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/40—Artificial lines; Networks simulating a line of certain length

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To settle the output potential of the receiving circuit to a constant value, by connecting series resistances between both ends of the matching terminating resistance, which is connected between two lines of the balanced transmission line, and differential input terminals of the receiving circuit and by applying the offset potential across differential input terminals. CONSTITUTION:One end of matching terminating resistance 5 is connected to differential input terminal 6 of receiving circuit 8 through series resistance 10. The other end of resistance 5 is connected to differential input terminal 7 of circuit 8 through series resistance 11. At the normal operation time, the signal level from transmission circuit 1 and the noise level generated on balanced transmission line 4 are attenuated by resistances 10 and 11. For the release of transmission line 4, the short-circuit fault, or the fault or power break of circuit 1, the output potential at output terminal 9 of circuit 8 is settled to a constant potential because a constant offset potential is applied across terminals 6 and 7 of circuit 8.
JP5508380A 1980-04-25 1980-04-25 Offset potential applying method Pending JPS56152357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5508380A JPS56152357A (en) 1980-04-25 1980-04-25 Offset potential applying method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5508380A JPS56152357A (en) 1980-04-25 1980-04-25 Offset potential applying method

Publications (1)

Publication Number Publication Date
JPS56152357A true JPS56152357A (en) 1981-11-25

Family

ID=12988813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5508380A Pending JPS56152357A (en) 1980-04-25 1980-04-25 Offset potential applying method

Country Status (1)

Country Link
JP (1) JPS56152357A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007020709A1 (en) * 2005-08-19 2007-02-22 Fujitsu Limited Semiconductor device
JP2009295681A (en) * 2008-06-03 2009-12-17 Sumitomo Electric Ind Ltd Laser diode driving circuit
JP2017194454A (en) * 2016-04-22 2017-10-26 新特系統股▲フン▼有限公司Ｓｙｎｃ−Ｔｅｃｈ Ｓｙｓｔｅｍ Ｃｏｒｐｏｒａｔｉｏｎ Probe card

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007020709A1 (en) * 2005-08-19 2007-02-22 Fujitsu Limited Semiconductor device
JP2009295681A (en) * 2008-06-03 2009-12-17 Sumitomo Electric Ind Ltd Laser diode driving circuit
JP2017194454A (en) * 2016-04-22 2017-10-26 新特系統股▲フン▼有限公司Ｓｙｎｃ−Ｔｅｃｈ Ｓｙｓｔｅｍ Ｃｏｒｐｏｒａｔｉｏｎ Probe card

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