WO2007020709A1

WO2007020709A1 - Semiconductor device

Info

Publication number: WO2007020709A1
Application number: PCT/JP2005/015153
Authority: WO
Inventors: Junko Nakamoto; Naoaki Naka
Original assignee: Fujitsu Limited
Priority date: 2005-08-19
Filing date: 2005-08-19
Publication date: 2007-02-22

Abstract

A first resistor is connected between a positive logic input terminal of an operational amplifier and a first potential. A second resistor is connected between a negative logic input of the operational amplifier and a second potential. A third resistor is connected between one of a pair of signal input terminals and the positive logic input terminal. A fourth resistor is connected between the other signal input terminal and the negative logic input terminal of the operational amplifier. A terminating resistor is connected between the paired signal input terminals. When the input is open, the potential difference between the ends of a circuit composed of the third resistor connected in series between the input terminals of the operational amplifier, the terminating resistor, and the fourth resistor is applied between the input terminals of the operational amplifier. With this, a stable potential difference is caused between the input terminals with a small consumption current compared to the prior art, and a stable output is obtained.

Description

Specification

Semiconductor device

Technical field

The present invention relates to a semiconductor device, and more particularly to a differential input buffer circuit suitable for use in a differential transmission system.

Background art

FIG. 10 shows a configuration of a conventional differential input buffer circuit.

As shown in FIG. 10, a conventional differential input buffer circuit 100 is configured by using an operational amplifier 101 and has a pair of signal input terminals INP1 and INN1.

[0003] Positive logic signal input terminal INP1 is connected to the positive logic input terminal of the operational amplifier 101 (non-inverting input terminal) INP2, and the negative logic signal input terminal INN1 is the negative logic input terminal of the operational amplifier 101 (inverting input terminal) Connected to INN2. Also, a termination resistor Rt corresponding to the transmission method is connected between the pair of signal input terminals INP 1 and INN1.

[0004] In the differential input buffer circuit, the differential signals input from the pair of signal input terminals INP1 and INN1 are input to the operational amplifier 101 via the respective transmission paths. Then, it is amplified by the operational amplifier 101 and output from the output terminal OUT.

Here, the differential input buffer circuit 100 shown in FIG. 10 is used, for example, in a receiving side device in a differential transmission system. In such a differential transmission system, communication is performed by connecting a transmitting device and a receiving device via a cable or the like. For example, when a cable or the like is removed, an input with no signal input to the receiving device is opened. It will end up in a state. As a result, the level of the signal input to the input terminals INP2 and INN2 of the operational amplifier 101 becomes unstable (for example, there is no level difference between the input signals), and the output signal from the output terminal OUT also becomes unstable.

[0006] Therefore, as one method for preventing the occurrence of the above-described problems when the input of the receiving device is open, a pair of signal input terminals INP1, I NN1 as shown in FIG. A method of connecting a pull-up resistor Ru and a pull-down resistor Rd is proposed (see, for example, Patent Document 1). [0007] According to this, even if the input is opened, the signal input terminals INP1 and INN1 of the differential input buffer circuit are fixed to a predetermined potential by the pull-up resistor Ru and the pull-down resistor Rd. Accordingly, it is possible to prevent the input to the operational amplifier 101 from being stabilized and the operation from becoming unstable.

[0008] Here, it is desirable that the potential difference between the input terminals INP2 and INN2 of the operational amplifier 101 by the pull-up resistor Ru and the pull-down resistor Rd is, for example, 10 mV to 20 mV. In addition, the larger the potential difference between the input terminals INP2 and INN2, the more stable the operation can be expected under the influence of noise.

However, a stable potential difference between the input terminals INP2 and INN2 (between the signal input terminals INP1 and INN1) using the pull-up resistor Ru and the pull-down resistor Rd as in the conventional example shown in FIG. In order to generate Voff set, the current 12 shown by the equation (1) is required.

I2 = (Voffset) / (Rt)

[0010] Normally, in the differential input buffer circuit, the resistance value of the termination resistor Rt provided between the transmission paths of the signals constituting the differential signal is relatively small. For example, in the LVDS (Low Voltage Differential Signaling) interface, the resistance value of the termination resistor Rt is 100 Ω (ohm). For this reason, the current 12 expressed by the above-described equation (1) is a large current.

[0011] When the pull-up resistor Ru and the pull-down resistor Rd are connected as in the conventional example shown in FIG. 10, transmission characteristics such as a transmission waveform and voltage are adversely affected when data transmission is performed. In other words, in a differential transmission system such as LVDS, transmission characteristics such as transmission waveform and voltage are standardized, but the transmission characteristics can be obtained by connecting pull-up resistor Ru and pull-down resistor Rd. May fall out of specification.

Patent Document 1: Japanese Patent Laid-Open No. 6-152658

Disclosure of the invention

An object of the present invention is to obtain a stable output with a small current consumption even when the input of a differential input buffer circuit is in an open state.

The semiconductor device of the present invention includes an operational amplifier, four resistors, and a termination resistor. One end of the first resistor is connected to the positive logic input terminal of the operational amplifier, and the first potential is supplied to the other end. The second resistor has one end connected to the negative logic input terminal of the operational amplifier and the other end connected to the second Is supplied. The third resistor is connected between one of the pair of signal input terminals of the semiconductor device and the positive logic input terminal of the operational amplifier. The fourth resistor is connected between the other of the pair of signal input terminals and the negative logic input terminal of the operational amplifier. The terminator is connected between a pair of signal input terminals.

[0015] According to the present invention, the third resistor, the terminating resistor, and the fourth resistor are connected in series between the positive logic input terminal and the negative logic input terminal of the operational amplifier. Therefore, when the input is open, the potential difference across the series circuit consisting of the third resistor, termination resistor, and fourth resistor is given between the input terminals of the operational amplifier. A stable potential difference can be generated between the input terminals with a small current consumption.

Brief Description of Drawings

FIG. 1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a specific configuration example of a semiconductor device according to a second embodiment.

FIG. 4 is a diagram showing a specific configuration example of the semiconductor device according to the second embodiment.

FIG. 5 is a diagram showing a configuration example of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a specific configuration example of the semiconductor device according to the third embodiment.

FIG. 7 is a diagram showing a specific configuration example of the semiconductor device according to the third embodiment.

FIG. 8 is a diagram showing a specific configuration example of the semiconductor device according to the third embodiment.

FIG. 9 is a diagram showing a configuration example of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of a conventional differential input buffer circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0018] (First embodiment)

FIG. 1 is a diagram showing a configuration example of a differential input canuffer circuit to which the semiconductor device according to the first embodiment of the present invention is applied. Note that the differential input buffer circuit in each of the first to third embodiments including the second and third embodiments described later is configured as one semiconductor device.

As shown in FIG. 1, the differential input buffer circuit 1 includes an operational amplifier 10 and four resistors R1, R2, R3, R4 and termination resistor Rt.

[0020] The pair of signal input terminals of the differential input buffer circuit 1 has a positive logic signal input terminal INP1 connected to the positive logic input terminal (non-inversion side input terminal) INP2 of the operational amplifier 10 via the resistor R3. The negative logic signal input terminal INN1 is connected to the negative logic input terminal (inverting input terminal) INN2 of the operational amplifier 10 through the resistor R4.

That is, one end of the resistor R3 is connected to the positive logic signal input terminal IN PI of the pair of signal input terminals, and the other end is connected to the positive logic input terminal INP2 of the operational amplifier 10. Similarly, one end of the resistor R4 is connected to the negative logic signal input terminal INN1 of the pair of signal input terminals, and the other end is connected to the negative logic input terminal INN2 of the operational amplifier 10.

[0022] It should be noted that the resistance values of the resistors R3 and R4 are preferably the same in order to prevent the transmission paths of the two signals constituting the differential signal from becoming unbalanced. The resistors R3 and R4 may also have a function as a protective resistor for preventing the occurrence of electrostatic breakdown in the operational amplifier 10 (more specifically, each element constituting the operational amplifier 10).

[0023] The resistor R1 is connected between the positive logic input terminal INP2 of the operational amplifier 10 and the signal line supplying the first potential VI, and the negative logic input terminal INN2 of the operational amplifier 10 and the second potential V2 are supplied. A resistor R2 is connected to the signal line to be connected.

Specifically, one end of the resistor R1 is connected to the interconnection point between the positive logic input terminal INP2 and the resistor R3 of the operational amplifier 10, and the first potential VI is supplied to the other end. Also, one end of the resistor R2 is connected to the interconnection point between the negative logic input terminal INN2 of the operational amplifier 10 and the resistor R4, and the second potential V2 is supplied to the other end.

[0025] Here, the first potential VI and the second potential V2 are different potentials. For example, the power supply voltage VDD may be used for the first potential V 1, and the reference potential VSS (ground level GND or the like) may be used for the second potential V 2. The first and second potentials VI and V2 are not limited to these and are arbitrary.

Further, a termination resistor Rt is connected between the pair of signal input terminals INP1 and INN1 of the differential input buffer circuit 1. Specifically, one end of the termination resistor Rt is connected to the interconnection point between the positive logic signal input terminal INP1 and the resistor R3, and the other end is connected to the interconnection point between the negative logic signal input terminal INN1 and the resistor R4. . This termination resistor Rt is, for example, a standard for differential transmission. It is determined by the case.

In the differential input buffer circuit 1 configured as described above, a pair of signal input terminals INP

1. The differential signals input from INN1 are input to the input terminals INP2 and INN2 of the operational amplifier 10 via resistors R3 and R4, respectively. Then, it is amplified by the operational amplifier 10 and output from the output terminal OUT.

[0028] Here, the connection line (cable, etc.) for inputting the differential signal is also removed from the pair of signal input terminals INP1 and INN1, and the input of the differential input canoffer circuit 1 is The case where it will be in an open state is demonstrated.

As shown in FIG. 1, in the differential input buffer circuit 1 according to the present embodiment, resistors Rl, R3, Rt, R4, and R2 are connected in series between the first potential VI and the second potential V2. It is connected to the. The positive logic input terminal INP2 of the operational amplifier 10 is connected to the interconnection point of the resistors R1 and R3, and the negative logic input terminal INN2 of the operational amplifier 10 is connected to the interconnection point of the resistors R4 and R2.

[0030] Therefore, when the input of the differential input buffer circuit 1 is in an open state, the input terminals INP2 and INN2 of the op-amp 10 are fixed at different predetermined potentials. Specifically, the input terminal INP2 of the operational amplifier 10 becomes the potential at the interconnection point of the resistors R1 and R3, and the input terminal INN2 of the operational amplifier 10 becomes the potential at the interconnection point of the resistors R4 and R2.

That is, a potential difference occurs between both ends of the resistors R 3, Rt, and R 4 connected in series between the input terminals INP 2 and INN 2 of the operational amplifier 10. Therefore, even if the input of the differential input buffer circuit 1 is in an open state, it is possible to prevent the input of the operational amplifier 10 from being stable and unstable.

Here, in the differential input buffer circuit shown in FIG. 1, if the potential difference between the input terminals INP2 and INN2 of the operational amplifier 10 necessary for obtaining a stable output from the output terminal OUT is Voff set, this potential difference In order to generate Voff set, the current II shown by Equation (2) is required.

11 = (Voffset) / (R3 + R4 + Rt),, (2)

[0033] As is clear from the above equation (1), the input terminals INP2 and INP of the operational amplifier 10 The current II for generating the potential difference Voff set between N2 is much smaller than the current 12 that has been required conventionally. Therefore, according to this embodiment, even if the input of the differential input buffer circuit is in an open state, a stable output can be obtained with a small current consumption.

[0034] Further, according to the present embodiment, the resistors Rl and R2 are connected between the terminating resistor Rt and the input terminals INP2 and INN2 of the operational amplifier 10 via the resistors R3 and R4. Thus, the resistance values of the resistors Rl and R2 can be increased, and the influence on the transmission characteristics such as the transmission waveform and voltage on the differential transmission system in data transmission can be suppressed.

[0035] (Second Embodiment)

Next, a second embodiment of the present invention will be described.

In the second embodiment described below, the resistors Rl and R2 in the first embodiment described above are configured by MOS (metal oxide semiconductor) transistors, respectively.

FIG. 2 is a diagram illustrating a configuration example of a differential input buffer circuit to which the semiconductor device according to the second embodiment is applied. In FIG. 2, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

In the differential input buffer circuit shown in FIG. 2, Ml and M2 are MOS transistors, which correspond to the resistors Rl and R2 in the first embodiment shown in FIG. That is, one of the source and drain of the MOS transistor Ml is connected to the positive logic input terminal I NP2 of the operational amplifier 10, and the first potential VI is supplied to the other. Similarly, one of the source and drain of the MOS transistor M2 is connected to the negative logic input terminal INN2 of the operational amplifier 10, and the second potential V2 is supplied to the other.

Since the operation of the differential input buffer circuit shown in FIG. 2 is the same as that of the first embodiment described above, description thereof is omitted.

[0039] Also in the second embodiment, when the input of the differential input buffer circuit is in an open state, the potential difference between both ends of the resistors R3, Rt, and R4 connected in series is between the input terminals INP2 and INN2 of the operational amplifier 10. Occurs. In addition, the current required to generate the potential difference Voff set between the input terminals INP2 and INN2 of the operational amplifier 10 is (Voff set) / (R3 + R4 + Rt). The That is, the same effect as that of the first embodiment described above can be obtained in the second embodiment. For example, even if the input of the differential input buffer circuit is in an open state, it is possible to stabilize the input of the operational amplifier 10 with a small current consumption to prevent the operation from becoming unstable, and to obtain a stable output.

FIG. 3 is a diagram illustrating an example of a specific configuration of the differential input canoffer circuit according to the second embodiment. In FIG. 3, constituent elements having the same functions as those shown in FIGS. 1 and 2 are given the same reference numerals, and redundant descriptions are omitted.

The differential input buffer circuit shown in FIG. 3 uses an N-channel MOS transistor NT1 as the data M2 in the differential input buffer circuit shown in FIG.

That is, one of the source and drain of the P-channel MOS transistor PT1 is connected to the positive logic input terminal INP2 of the op amp 10, and the first potential VI is supplied to the other. The control voltage VC1 is supplied to the gate of the P-channel MOS transistor PT1.

Similarly, one of the source and the drain of the N-channel MOS transistor NT1 is connected to the negative logic input terminal INN2 of the op amp 10, and the second potential V2 is supplied to the other. The control voltage VC2 is supplied to the gate of the N-channel MOS transistor NT1.

[0044] In the differential input buffer circuit shown in Fig. 3, MOS transistors PT1 and NT1 corresponding to resistors Rl and R2 are used as switching elements, and MOS transistors PT1 and NT1 are controlled on the user side by control voltages VC1 and VC2. It becomes possible to control. Note that any voltage may be supplied as the control voltages V Cl and VC2 depending on the use situation or the like.

FIG. 4 is a diagram showing another example of a specific configuration of the differential input canoffer circuit according to the second embodiment. In FIG. 4, components having the same functions as those shown in FIGS. 1 and 2 are given the same reference numerals, and redundant descriptions are omitted.

The differential input buffer circuit shown in FIG. 4 uses N-channel MOS transistors NT2 and NT3 as MOS transistors M1 and M2 in the differential input buffer circuit shown in FIG.

That is, one of the source and drain of the N-channel MOS transistor NT2 is connected to the positive logic input terminal INP2 of the op amp 10, and the first potential VI is supplied to the other. Ma The control voltage VC3 is supplied to the gate of the N-channel MOS transistor NT2.

Similarly, one of the source and drain of the N-channel MOS transistor NT3 is connected to the negative logic input terminal INN2 of the op amp 10, and the second potential V2 is supplied to the other. The control voltage VC4 is supplied to the gate of the N-channel MOS transistor NT3.

[0049] In the differential input buffer circuit shown in Fig. 4, MOS transistors NT2 and NT3 corresponding to resistors Rl and R2 are used as switching elements, and MOS transistors NT2 and NT3 are controlled on the user side by control voltages VC3 and VC4. It becomes possible to control. As the control voltages V C3 and VC4, any voltage may be supplied according to the usage situation. It becomes easy.

[0050] (Third embodiment)

Next, a third embodiment of the present invention will be described.

In the third embodiment described below, the resistors R3 and R4 in the first embodiment described above are configured by MOS transistors, respectively.

FIG. 5 is a diagram illustrating a configuration example of a differential input buffer circuit to which the semiconductor device according to the third embodiment is applied. In FIG. 5, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

In the differential input buffer circuit shown in FIG. 5, M3 and M4 are MOS transistors, and correspond to the resistors R3 and R4 in the first embodiment shown in FIG. That is, the positive logic signal input terminal INP1 and the positive logic input terminal INP2 of the operational amplifier 10 are connected via the MOS transistor M3, and the negative logic signal input terminal INN1 and the negative logic input terminal INN2 of the operational amplifier 10 are connected via the MOS transistor M4. Connected.

Specifically, one of the source and drain of the MOS transistor M3 is connected to the positive logic signal input terminal INP1, and the other is connected to the positive logic input terminal INP2 of the operational amplifier 10. Similarly, one of the source and drain of the MOS transistor M4 is connected to the negative logic signal input terminal INN1, and the other is connected to the negative logic input terminal INN2 of the operational amplifier 10.

Since the operation of the differential input buffer circuit shown in FIG. 5 is the same as that of the first embodiment described above, description thereof is omitted. Also in the third embodiment, when the input of the differential input buffer circuit is in an open state, a potential difference is generated between the input terminals INP2 and INN2 of the operational amplifier 10 due to the MOS transistors M3 and M4 and the termination resistor Rt. If the resistance values of the MOS transistors M3 and M4 are R3, R4 ', the current required to generate the potential difference Voffset between the input terminals INP2 and INN2 of the operational amplifier 10 is (Voffset) / (R3' + R4, + Rt). Therefore, the same effects as those of the first embodiment described above can be obtained in the third embodiment.

FIG. 6 is a diagram illustrating an example of a specific configuration of the differential input canffer circuit according to the third embodiment. In FIG. 6, constituent elements having the same functions as those shown in FIGS. 1 and 5 are given the same reference numerals, and redundant descriptions are omitted.

The differential input buffer circuit shown in FIG. 6 uses N-channel MOS transistors NT4 and NT5 as the MOS transistors M3 and M4 in the differential input buffer circuit shown in FIG.

That is, one of the source and drain of the N-channel MOS transistor NT4 is connected to the positive logic signal input terminal INP1, and the other is connected to the positive logic input terminal INP2 of the operational amplifier 10. Similarly, one of the source and drain of the N-channel MOS transistor NT5 is connected to the negative logic signal input terminal INN1, and the other is connected to the negative logic input terminal INN2 of the operational amplifier 10.

[0059] Here, in order to prevent the transmission paths of the two signals constituting the differential signal from becoming unbalanced as described above, the resistance values of the N-channel MOS transistors NT4 and NT5 must be the same. Is desirable. Therefore, N-channel MOS transistors NT4 and NT5 are composed of transistors having the same characteristics, and the same control voltage VC5 is supplied to each gate.

In the differential input buffer circuit shown in FIG. 6, the MOS transistors NT4 and NT5 corresponding to the resistors R3 and R4 are used as switching elements, and can be controlled by the control voltage VC5 on the user side. In addition, using only an N-channel MOS transistor as the MOS transistor facilitates manufacturing.

FIG. 7 is a diagram showing another example of a specific configuration of the differential input canoffer circuit according to the third embodiment. In FIG. 7, constituent elements having the same functions as those shown in FIGS. 1 and 5 are given the same reference numerals, and redundant descriptions are omitted. The differential input buffer circuit shown in FIG. 7 uses P-channel MOS transistors PT2 and PT3 as the MOS transistors M3 and M4 in the differential input buffer circuit shown in FIG.

That is, one of the source and drain of the Ρchannel MOS transistor ΡΤ2 is connected to the positive logic signal input terminal INP1, and the other is connected to the positive logic input terminal ΙΝΡ2 of the operational amplifier 10. Similarly, one of the source and drain of the channel MOS transistor ΡΤ3 is connected to the negative logic signal input terminal INN1, and the other is connected to the negative logic input terminal ΙΝΝ2 of the operational amplifier 10.

Here, in order to prevent the transmission paths of the two signals constituting the differential signal from becoming unbalanced as described above, the resistance values indicated by the Ρchannel MOS transistors ΡΤ2 and ΡΤ3 must be the same. desirable. Therefore, Ρchannel MOS transistors ΡΤ2 and ΡΤ3 are composed of transistors having the same characteristics, and the same control voltage VC6 is supplied to each gate.

In the differential input buffer circuit shown in FIG. 7, the MOS transistors PT2 and ΡΤ3 corresponding to the resistors R3 and R4 are used as switching elements, and can be controlled on the user side by the control voltage VC6.

FIG. 8 is a diagram showing another example of a specific configuration of the differential input canoffer circuit according to the third embodiment. In FIG. 8, components having the same functions as those shown in FIGS. 1 and 5 are given the same reference numerals, and redundant descriptions are omitted.

[0067] The differential input buffer circuit shown in FIG. 8 includes one Ν-channel MOS transistor ΝΤ6 and ΝΤ7 and one Ρ-channel MOS transistor として 4, as MOS transistors Μ3 and Μ4 in the differential input buffer circuit shown in FIG. This uses a pass transistor consisting of ΡΤ5.

[0068] Specifically, a pair of Νchannel Μ OS transistor ΝΤ6 and Ρchannel MOS transistor ΡΤ4 in which the sources are connected and the drains are connected is the positive logic signal input terminal INP1 and the operational amplifier 10 positive logic. Connected to the input terminal INP2. Similarly, a combination of an N-channel MOS transistor NT7 and a P-channel MOS transistor PT5, whose sources are connected and their drains are connected. Negative logic signal input terminal INN1 and negative logic input terminal of operational amplifier 10 INN2 Connected between. [0069] Further, N-channel MOS transistors NT6 and NT7 are composed of transistors having the same characteristics so that each pass transistor has the same resistance value, and the same control voltage VC7 is supplied to each gate. Transistors PT4 and ΡΤ5 are composed of transistors with the same characteristics, and the same control voltage VC8 is supplied to each gate. This prevents the transmission paths of the two signals that make up the differential signal from becoming unbalanced.

[0070] (Fourth embodiment)

Next, a fourth embodiment of the present invention will be described.

In the first to third embodiments described above, the differential input buffer circuit is configured as one semiconductor device. However, the fourth embodiment described below is a terminal in the differential input buffer circuit. A resistor is provided outside the semiconductor device in which other elements in the differential input buffer circuit are configured.

FIG. 9 is a diagram illustrating a configuration example of a differential input buffer circuit to which the semiconductor device according to the fourth embodiment is applied. In FIG. 9, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

In the differential input buffer circuit shown in FIG. 9, the elements included in the broken line frame la are formed as one semiconductor device. Rta is a termination resistor connected between the pair of signal input terminals IN Pl and INN1, and corresponds to the termination resistor Rt in the first embodiment shown in FIG. That is, one end of the termination resistor Rta is connected to the interconnection point between the positive logic signal input terminal INP 1 and the resistor R3, and the other end is connected to the interconnection point between the negative logic signal input terminal INN1 and the resistor R4.

Note that the differential input buffer circuit shown in FIG. 9 is the same in configuration and operation as the first embodiment described above except that the termination resistor Rta is provided outside the semiconductor device. is there.

Therefore, also in the fourth embodiment, the same effect as in the first embodiment described above can be obtained. Furthermore, by providing the termination resistor Rta in the differential input buffer circuit outside the semiconductor device, it is possible to reduce the characteristic variation in the termination resistor Rta and improve the accuracy, and to change it on the user side. Become.

In FIG. 9, the differential input buffer circuit in the first embodiment shown in FIG. Although the case where the termination resistance of the path is provided outside the semiconductor device is shown as an example, similarly, the termination resistance of the differential input buffer circuit in the second and third embodiments is provided outside the semiconductor device. Also good.

Further, in each of the above-described embodiments, the force using a MOS transistor as a transistor used instead of a resistor is not limited to this. As a transistor used in place of the resistor, for example, an arbitrary field effect transistor (FET) can be applied.

[0077] In addition, each of the above-described embodiments is merely an example of a specific example for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. Is. That is, the present invention can be implemented in various forms without departing from the technical idea or the main characteristic power thereof.

Industrial applicability

As described above, according to the present invention, when the input is in an open state, the third resistor, the termination resistor, and the fourth resistor connected in series with respect to the input terminals of the operational amplifier. As a result, a stable potential difference can be generated between the input terminals of the operational amplifier between the input terminals of the operational amplifier with a smaller current consumption than in the past. As a result, even when the input is in an open state, a stable output can be obtained with a small current consumption.

Claims

The scope of the claims

[1] A semiconductor device having a pair of signal input terminals,

An operational amplifier,

A first resistor having one end connected to the positive logic input terminal of the operational amplifier and a first potential supplied to the other end;

A second resistor having one end connected to the negative logic input terminal of the operational amplifier and a second potential different from the first potential supplied to the other end;

A third resistor having one end connected to the positive logic input terminal of the operational amplifier and the other end connected to one of the pair of signal input terminals;

A fourth resistor having one end connected to the negative logic input terminal of the operational amplifier and the other end connected to the other of the pair of signal input terminals;

A semiconductor device comprising: a terminating resistor connected between the other ends of the third and fourth resistors.

2. The semiconductor device according to claim 1, wherein the first resistor is constituted by a first transistor, and the second resistor is constituted by a second transistor.

3. The semiconductor device according to claim 2, wherein the first transistor is a P-channel MOS transistor, and the second transistor is an N-channel MOS transistor.

4. The semiconductor device according to claim 2, wherein the first and second transistors are N-channel MOS transistors.

5. The semiconductor device according to claim 2, wherein resistance values of the first and second resistors can be controlled.

6. The semiconductor device according to claim 1, wherein the third resistor is constituted by a first transistor, and the fourth resistor is constituted by a second transistor.

7. The semiconductor device according to claim 6, wherein the first and second transistors are N-channel MOS transistors.

8. The semiconductor device according to claim 6, wherein the first and second transistors are P-channel MOS transistors.

[9] The first and second transistors each have a source connected to each other and a drain. 7. The semiconductor device according to claim 6, wherein the semiconductor device is a pair of N-channel MOS transistor and P-channel MOS transistor connected to each other.

10. The semiconductor device according to claim 6, wherein the resistance values of the third and fourth resistors can be controlled.

[11] The semiconductor device according to [1], wherein the third and fourth resistors also serve as protective resistors for preventing electrostatic breakdown.

[12] The termination resistor is provided outside the semiconductor device constituting the semiconductor device except for the termination resistor, and the termination resistor is connected between transmission paths connected to the pair of signal input terminals. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed.

[13] A semiconductor device having a pair of signal input terminals,

An operational amplifier,

A third resistor having one end connected to the positive logic input terminal or negative logic input terminal of the operational amplifier and the other end connected to one of the pair of signal input terminals;

A semiconductor device comprising: a termination resistor having one end connected to the other end of the third resistor and the other end connected to the other of the pair of signal input terminals.

[14] A semiconductor device having a pair of signal input terminals,

A first resistor, a second resistor, a termination resistor, a third resistor connected in series between a signal line that supplies a first potential and a signal line that supplies a second potential different from the first potential. And the fourth resistor,

A positive logic input terminal is connected to the interconnection point between the first resistor and the second resistor, and a negative logic input terminal is connected to the interconnection point between the third resistor and the fourth resistor. With an amplifier,

An interconnection point between the second resistor and the termination resistor, and an interconnection point between the third resistor and the termination resistor are connected to the pair of signal input terminals. Body equipment.

The first resistor and the fourth resistor may be used as a set, and the second resistor and the third resistor may be used as a set. At least one of the resistors may be configured by a field effect transistor. 15. The semiconductor device according to claim 14, wherein: