JPS5776853A - Testing method for semiconductor wafer - Google Patents

Testing method for semiconductor wafer

Info

Publication number
JPS5776853A
JPS5776853A JP15259280A JP15259280A JPS5776853A JP S5776853 A JPS5776853 A JP S5776853A JP 15259280 A JP15259280 A JP 15259280A JP 15259280 A JP15259280 A JP 15259280A JP S5776853 A JPS5776853 A JP S5776853A
Authority
JP
Japan
Prior art keywords
chips
sheets
processing unit
central processing
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15259280A
Other languages
Japanese (ja)
Inventor
Yasushi Matsukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15259280A priority Critical patent/JPS5776853A/en
Publication of JPS5776853A publication Critical patent/JPS5776853A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Abstract

PURPOSE:To shorten total testing time by testing all chips of wafers sampled from a lot and omitting the test of chips, relative positions thereof are the same as chips recognized as acceptables through the test. CONSTITUTION:S Sheets are sampled from N sheets, all chips of the S sheets are measured by means of a testing device 1 and test results are transmitted to a wafer prober 2 and a central processing unit 4. The central processing unit 4 reads the positional coordinates of the chips from the wafer prober 2 through a position controlling interface 3, and houses the test results in a memory strage 5. The central processing unit 4 inspects the results of said housing, and (N-S) sheets are not measured about the chips at the positions of acceptables. Accordingly, the total testing time of one lot is shortened.
JP15259280A 1980-10-30 1980-10-30 Testing method for semiconductor wafer Pending JPS5776853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15259280A JPS5776853A (en) 1980-10-30 1980-10-30 Testing method for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15259280A JPS5776853A (en) 1980-10-30 1980-10-30 Testing method for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS5776853A true JPS5776853A (en) 1982-05-14

Family

ID=15543803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15259280A Pending JPS5776853A (en) 1980-10-30 1980-10-30 Testing method for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS5776853A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254626A (en) * 1984-05-30 1985-12-16 Sharp Corp Wafer testing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254626A (en) * 1984-05-30 1985-12-16 Sharp Corp Wafer testing method

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