JPS5775431A - Formation of pattern - Google Patents

Formation of pattern

Info

Publication number
JPS5775431A
JPS5775431A JP15118480A JP15118480A JPS5775431A JP S5775431 A JPS5775431 A JP S5775431A JP 15118480 A JP15118480 A JP 15118480A JP 15118480 A JP15118480 A JP 15118480A JP S5775431 A JPS5775431 A JP S5775431A
Authority
JP
Japan
Prior art keywords
taper
resist
etching
pattern
treated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15118480A
Other languages
Japanese (ja)
Inventor
Tsukane Hirokawa
Yasuo Arima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15118480A priority Critical patent/JPS5775431A/en
Publication of JPS5775431A publication Critical patent/JPS5775431A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To form taper in a layer to be treated, and to prevent disconnection of a semiconductor device by a method wherein a photo resist pattern is heat treated to form taper at the circumferential edge thereof, and reactive ion etching is performed. CONSTITUTION:The resist mask 12 is provided on PSG11 on an SI substrate 10, and heat treatment is performed to form taper at the side of pattern. The inclining angle of taper can be changed according to the kind of resist and heat treatment, and when various kind of resist having different sensitivity is applied, taper of various angle can be obtained. Mixed gas of CHF3 and O2 is used, the flow rate of O2 gas is selected, the etching ratios of PSG and the resist having equal film thickness are equalized, and when etching is performed, an opening having taper of the same shape with taper of the resist pattern 12 can be formed in PSG11, and the same time the resist mask 12 is incinerated to be removed. When thickness, etching rate of the resist mask and the layer to be treated are varied respectively, various taper shape can be formed, and disconnection at the step part can be prevented.
JP15118480A 1980-10-28 1980-10-28 Formation of pattern Pending JPS5775431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15118480A JPS5775431A (en) 1980-10-28 1980-10-28 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15118480A JPS5775431A (en) 1980-10-28 1980-10-28 Formation of pattern

Publications (1)

Publication Number Publication Date
JPS5775431A true JPS5775431A (en) 1982-05-12

Family

ID=15513113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15118480A Pending JPS5775431A (en) 1980-10-28 1980-10-28 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS5775431A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582029A (en) * 1981-06-26 1983-01-07 Seiko Epson Corp Etching method for insulating film on semiconductor substrate
JPS5984529A (en) * 1982-11-08 1984-05-16 Nippon Denso Co Ltd Forming method of pattern
JPS6053073A (en) * 1983-09-02 1985-03-26 Hitachi Ltd Solid-state image pickup element with microlens and manufacture thereof
JPS6060757A (en) * 1983-09-14 1985-04-08 Hitachi Ltd Image pickup element with microlens and manufacture thereof
JPS6060756A (en) * 1983-09-14 1985-04-08 Hitachi Ltd Solid-state image pickup element with microlens and manufacture thereof
JPS611028A (en) * 1984-05-18 1986-01-07 Fujitsu Ltd Manufacture of semiconductor device
JPS611027A (en) * 1984-05-18 1986-01-07 Fujitsu Ltd Manufacture of semiconductor device
US4824747A (en) * 1985-10-21 1989-04-25 General Electric Company Method of forming a variable width channel
US4837775A (en) * 1985-10-21 1989-06-06 General Electric Company Electro-optic device having a laterally varying region
JPH04266027A (en) * 1990-10-29 1992-09-22 Gold Star Co Ltd Method for oblique etching
JP2003029297A (en) * 2001-07-13 2003-01-29 Nec Kagoshima Ltd Active matrix substrate and method of manufacturing the same

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582029A (en) * 1981-06-26 1983-01-07 Seiko Epson Corp Etching method for insulating film on semiconductor substrate
JPS5984529A (en) * 1982-11-08 1984-05-16 Nippon Denso Co Ltd Forming method of pattern
JPH045260B2 (en) * 1982-11-08 1992-01-30
JPH0512864B2 (en) * 1983-09-02 1993-02-19 Hitachi Ltd
JPS6053073A (en) * 1983-09-02 1985-03-26 Hitachi Ltd Solid-state image pickup element with microlens and manufacture thereof
JPS6060757A (en) * 1983-09-14 1985-04-08 Hitachi Ltd Image pickup element with microlens and manufacture thereof
JPS6060756A (en) * 1983-09-14 1985-04-08 Hitachi Ltd Solid-state image pickup element with microlens and manufacture thereof
JPH0570944B2 (en) * 1983-09-14 1993-10-06 Hitachi Ltd
JPS611028A (en) * 1984-05-18 1986-01-07 Fujitsu Ltd Manufacture of semiconductor device
JPS611027A (en) * 1984-05-18 1986-01-07 Fujitsu Ltd Manufacture of semiconductor device
JPH037146B2 (en) * 1984-05-18 1991-01-31 Fujitsu Ltd
JPH037145B2 (en) * 1984-05-18 1991-01-31 Fujitsu Ltd
US4837775A (en) * 1985-10-21 1989-06-06 General Electric Company Electro-optic device having a laterally varying region
US4824747A (en) * 1985-10-21 1989-04-25 General Electric Company Method of forming a variable width channel
JPH04266027A (en) * 1990-10-29 1992-09-22 Gold Star Co Ltd Method for oblique etching
JP2003029297A (en) * 2001-07-13 2003-01-29 Nec Kagoshima Ltd Active matrix substrate and method of manufacturing the same

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