JPS5766643A - Pattern forming method by lift-off - Google Patents

Pattern forming method by lift-off

Info

Publication number
JPS5766643A
JPS5766643A JP14181780A JP14181780A JPS5766643A JP S5766643 A JPS5766643 A JP S5766643A JP 14181780 A JP14181780 A JP 14181780A JP 14181780 A JP14181780 A JP 14181780A JP S5766643 A JPS5766643 A JP S5766643A
Authority
JP
Japan
Prior art keywords
layer
selected material
etching
carrying
lift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14181780A
Other languages
English (en)
Inventor
Takeshi Abe
Yoichiro Miyaguchi
Akihiro Shindo
Yoji Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP14181780A priority Critical patent/JPS5766643A/ja
Publication of JPS5766643A publication Critical patent/JPS5766643A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
JP14181780A 1980-10-09 1980-10-09 Pattern forming method by lift-off Pending JPS5766643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14181780A JPS5766643A (en) 1980-10-09 1980-10-09 Pattern forming method by lift-off

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14181780A JPS5766643A (en) 1980-10-09 1980-10-09 Pattern forming method by lift-off

Publications (1)

Publication Number Publication Date
JPS5766643A true JPS5766643A (en) 1982-04-22

Family

ID=15300810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14181780A Pending JPS5766643A (en) 1980-10-09 1980-10-09 Pattern forming method by lift-off

Country Status (1)

Country Link
JP (1) JPS5766643A (ja)

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