JPS5763841A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS5763841A JPS5763841A JP13959080A JP13959080A JPS5763841A JP S5763841 A JPS5763841 A JP S5763841A JP 13959080 A JP13959080 A JP 13959080A JP 13959080 A JP13959080 A JP 13959080A JP S5763841 A JPS5763841 A JP S5763841A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- film
- silicon
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
- 239000012535 impurity Substances 0.000 abstract 2
- 238000000926 separation method Methods 0.000 abstract 2
- 229910020489 SiO3 Inorganic materials 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13959080A JPS5763841A (en) | 1980-10-06 | 1980-10-06 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13959080A JPS5763841A (en) | 1980-10-06 | 1980-10-06 | Preparation of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5763841A true JPS5763841A (en) | 1982-04-17 |
| JPS6155250B2 JPS6155250B2 (enrdf_load_stackoverflow) | 1986-11-27 |
Family
ID=15248804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13959080A Granted JPS5763841A (en) | 1980-10-06 | 1980-10-06 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5763841A (enrdf_load_stackoverflow) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58199537A (ja) * | 1982-05-14 | 1983-11-19 | Matsushita Electric Ind Co Ltd | 高抵抗半導体層の製造方法 |
| US4583282A (en) * | 1984-09-14 | 1986-04-22 | Motorola, Inc. | Process for self-aligned buried layer, field guard, and isolation |
| US4948742A (en) * | 1987-09-08 | 1990-08-14 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device |
| US4997786A (en) * | 1986-06-13 | 1991-03-05 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a semiconductor device having buried insulation layer separated by ditches |
| US5372952A (en) * | 1992-04-03 | 1994-12-13 | National Semiconductor Corporation | Method for forming isolated semiconductor structures |
-
1980
- 1980-10-06 JP JP13959080A patent/JPS5763841A/ja active Granted
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58199537A (ja) * | 1982-05-14 | 1983-11-19 | Matsushita Electric Ind Co Ltd | 高抵抗半導体層の製造方法 |
| US4583282A (en) * | 1984-09-14 | 1986-04-22 | Motorola, Inc. | Process for self-aligned buried layer, field guard, and isolation |
| US4997786A (en) * | 1986-06-13 | 1991-03-05 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a semiconductor device having buried insulation layer separated by ditches |
| US4948742A (en) * | 1987-09-08 | 1990-08-14 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device |
| US5372952A (en) * | 1992-04-03 | 1994-12-13 | National Semiconductor Corporation | Method for forming isolated semiconductor structures |
| US5376560A (en) * | 1992-04-03 | 1994-12-27 | National Semiconductor Corporation | Method for forming isolated semiconductor structures |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6155250B2 (enrdf_load_stackoverflow) | 1986-11-27 |
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