JPS575136A - Timing generating circuit - Google Patents

Abstract

PURPOSE:To attain high precision, to reduce the quantity of hardware and to generate an optional timing pulse, by changing over delay times by a counter and a coincidence detecting means for a counter output and comparison data. CONSTITUTION:Counting is carried out with an external input clock C and only when a counting signal CO coincides with information M1 stored in a shift register 2 and an FF6 is reset, a coincidence detecting circuit 4 outputs a set signal (s) to output a set signal SO. Further, only when stored information M2 in a register 3 coincides with a counting signal CO and the FF6 is set, a reset signal R is outputted and the outputting of a set state signal SO is stopped. The set state signal SO from the FF6 is inputted to a delay circuit 7 and delay times are changed with a delay control signal DC to output a timing signal T with excellent setting precision. For this purpose, optional values are stored in the registers 2 and 3 to generate optional timing, and the delay circuit 7 performs minute-time delay, thus generating precise timing.