JPH0532763B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a system clock for supplying a phase-adjusted clock signal and a stop signal to each clock-operated system element device in a data processing system or the like. Regarding the control method,
In particular, the present invention relates to a method for reliably and easily adjusting signal delay time differences between system element devices.

[Technology background]

Data processing systems generally consist of a large number of devices, such as CPUs and peripheral devices, and many of these devices use common clock and stop signals to facilitate signal interface with each other. As a result, their movements are now controlled. In other words, each device is supplied with a clock signal and a stop signal that are common to the system, and each device identifies whether the clock signal is valid or invalid by matching the clock signal and the stop signal (logical product), and determines whether the clock signal is valid or invalid. In this case, the operation is stopped.

FIG. 1 is a conceptual diagram for explaining a conventional system clock control method. In the figure, 1 to 3 are clock-operated system element devices, 4 is a clock signal distribution device, 5 is a stop signal distribution device, 6 is a clock oscillator, 7 is a stop signal generation source, and DLA ₁ , DLA ₂ , and DLA ₃ are Clock signal delay circuits, DLB ₁ , DLB ₂ , DLB ₃ are stop signal delay circuits, CK ₁ , CK ₂ , CK ₃ are clock signals, SP ₁ ,
SP ₂ and SP ₃ indicate stop signals.

There are differences in distance between each system element device 1, 2, and 3 and the clock signal distribution device 4 and stop signal distribution device 5, that is, differences in cable length,
Due to differences in the electrical characteristics of the devices themselves, there are also differences in delay times during pulse transmission, which often reach tens of nanoseconds, for example.

For this reason, conventionally, as shown in the figure, each of the clock signal distribution device 4 and the stop signal distribution device 5 is provided with a system that compensates for the absolute pulse delay time difference between each element device to which the signal is to be distributed. Delay circuits DLA ₁ , DLA ₂ , DLA ₃ , and DLB ₁ ,
DLB ₂ and DLB ₃ were inserted to perform phase adjustment to synchronize the distributed signals.

However, in this case, each delay circuit must have a structure in which the amount of delay is variable, and the adjustable range must be at least greater than the maximum amount of pulse delay time difference that exists between the above-mentioned element devices,
Since the adjustment range is large, the adjustment becomes critical, making the work difficult and increasing skew.

[Object and structure of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a means for reliably facilitating phase adjustment when distributing clock and stop signals to a plurality of clock actuators having different pulse delay times, so that the variable delay circuits used are This system realizes a system clock control method that requires a smaller adjustment range than conventional systems.

For this reason, the present invention provides that in the delay of a clock signal, a delay of more than one clock period, that is, a unit machine cycle time, is unnecessary due to the continuity of the clock, and that in the delay of a stop signal, a delay in units of machine cycle time is unnecessary. This method focuses on the fact that it can be easily obtained by using a shift register, etc., and its configuration includes a plurality of clock operating devices and a clock signal and instructing the plurality of clock operating devices to enable or disable the clock signal. A system clock control method in a system having a clock signal distribution device and a stop signal distribution device, each of which distributes a stop signal having a wider pulse width than a clock signal to control the operation and stop of a clock actuating device. The clock signal distribution device includes means for adjusting the delay amount of the clock signal within a unit machine cycle time for each clock operation device, and the stop signal distribution device includes means for adjusting the amount of delay of the clock signal within a unit machine cycle time for each clock operation device, and the stop signal distribution device includes means for adjusting the amount of delay of the clock signal within a unit machine cycle time for each clock operation device. It includes means for separately adjusting the amount of delay per unit and the amount of delay within a unit machine cycle time, and the length of the signal line between the clock signal distribution device and stop signal distribution device and each clock operating device is the shortest. and the clock signal to each clock actuator is
Phase matching is achieved by adjusting the delay amount of each clock signal within the unit machine cycle time within the clock signal distribution device, and the stop signal to each clock operating device is adjusted within the machine cycle time within the stop signal distribution device. The phase is matched by combining the delay amount adjustment in integer multiples and the delay amount within the unit machine cycle time, and each clock operating device detects the presence of the stop signal by matching the input clock signal and the stop signal. This is characterized in that the clock signal is valid during this period.

[Embodiments of the invention]

First, the principle of the present invention will be explained with reference to FIG.

Figures 2a and 2b show two clock signals with a phase difference TD ₁ caused by pulse delay.
The machine cycle time is represented by 〓, and corresponding pulses in both clock signals are shown with the same symbols A, B, C, . . . . in this case,
The true phase difference between the two clock signals a and b is
TD ₁ , but in practice it is clear that it is sufficient to adjust the phase of TD ₂ , and generally TD ₁ >
Since 〓 and 〓＞TD ₂ , conventionally,
Compared to the phase adjustment of TD ₁ , the phase adjustment of TD ₂ can be done within a small range.

In addition, c and d in Fig. 2 are two with a phase difference TD ₃ .
It shows two stop signals. Phase difference shown
TD ₃ can be decomposed into 2 units of machine cycle time 2〓 and TD ₄ which is smaller than 〓, and the phase difference of 2〓 is
This can be easily achieved by shifting by two steps with a clock-driven shift register, so the variable delay circuit only needs to be able to adjust TD ₄ , and as in the case of the phase adjustment of the clock signal described above, it can be adjusted within a small range. This can be done by simply adjusting the phase.

Next, examples of the present invention will be shown.

FIG. 3 is a block diagram of one embodiment of a clock signal distribution device based on the present invention.
Only the phasing mechanism for one system element device is shown. In the figure, 8 indicates one of the clock-operated system elements. 9 is a clock signal distribution device; 11, 12, and 13 are clock oscillators with different frequencies, for example, 1 MHz, 2 MHz, and 3 MHz; 14 is a selector for selecting clock signals of different frequencies; and 15, 16, and 17 are respective phases. Each clock oscillator 1 with corresponding adjustment range
This is a variable delay circuit DL whose time is smaller than 1, 12, and 13 machine cycle times. 18 is selector 14
This is a selector that selects a clock signal of a different frequency in synchronization with the clock signal.

FIG. 4 is a block diagram of one embodiment of a stop signal distribution device based on the present invention.
Only the phasing mechanism for one system element device is shown. In the figure, 19 is one of the system element devices, 20 is a stop signal distribution device, 21 is a stop signal generation source, and 22 is a shift register.
Reference numerals 23, 24, and 25 are variable delay circuits DL whose respective phase adjustment ranges are smaller than the respective machine cycle times of the three different frequency clock signals shown in FIG. Reference numeral 26 denotes a selector for selecting the delay time of the stop signal corresponding to the clock signals of the three different frequencies.

If the shift register 22 is composed of n stages, a maximum delay time of n〓 can be obtained, and by taking out a signal from any intermediate stage, n〓 can be obtained.
An arbitrary delay time can be obtained in units of 〓 below. This and variable delay circuits 23, 24, 25
By combining these, it is possible to easily adjust a wide range of phase differences with high precision.

The above-described clock signal distribution device and stop signal distribution device provide phase-adjusted clock and stop signals to all clock-operated system elements.

In addition, GATED CLOCK is set on the system element device side.
When using the clock signal, the logical AND of the clock signal and the stop signal is used. In this case, phase adjustment is performed in the distribution device while observing each system element device so that the clock signal is not lost.

〔Effect of the invention〕

As described above, according to the method of the present invention, the delay amount adjustment in machine cycle time units for the stop signal can be easily performed using a shift register, etc., so that the work required for phase adjustment of the clock signal and the stop signal is reduced. In practice, the amount of delay is adjusted only within the machine cycle time, making it possible to reduce the work load and shorten the adjustment time. This also makes it possible to distribute the clock signal with a highly accurate phase, while for the stop signal, the phase adjustment range is large, so the skew error is slightly sweeter than for the clock signal, but the pulse width of the stop signal is Since it is wider than the clock signal and it is easier to match the two, the skew effect of the stop signal can be reduced, so overall clock control accuracy is improved, especially when applied to recent large computers that use high frequency clocks. , a great effect can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of the conventional system, Fig. 2 is an explanatory diagram of the principle of the present invention, and Fig. 3 is a diagram of a clock signal distribution device.
Embodiment Configuration Diagram FIG. 4 is an embodiment configuration diagram of a stop signal distribution device. In the figure, 8 and 19 are system element devices, 9 is a clock signal distribution device 11 to 13 are clock oscillators, 14, 18, and 26 are selectors, and 15, 1
6, 17, 23, 24, 25 are variable delay circuits, 2
1 is a stop signal generation source, and 22 is a shift register.

Claims (1)

[Claims] 1 A plurality of clock actuators and a stop signal which instructs the plurality of clock actuators to enable or disable the clock signal and which has a wider pulse width than the clock signal are distributed to each of the plurality of clock actuators to control the clock actuators. A system clock control method in a system having a clock signal distribution device and a stop signal distribution device for controlling operation and stop, wherein the clock signal distribution device distributes a clock signal within a unit machine cycle time for each clock operating device. The stop signal distribution device includes means for separately adjusting the delay amount of the stop signal in units of machine cycle time and the amount of delay within unit machine cycle time for each clock operating device. The length of the signal line between the clock signal distribution device and stop signal distribution device and each clock operating device is minimized, and the clock signal to each clock operating device is connected within the clock signal distribution device. The phase is matched by adjusting the delay amount of the clock signal within the unit machine cycle time, and the stop signal to each clock operating device is adjusted by adjusting the delay amount by an integral multiple of the machine cycle time in the stop signal distribution device. Phase matching is performed by combining the amount of delay within a unit machine cycle time, and each clock operating device makes the clock signal valid during the period in which the stop signal exists by matching the input clock signal with the stop signal. A system clock control method characterized by: