SU1569797A2 - Standard time signal selector - Google Patents

Abstract

The invention relates to the field of instrumentation and can be used in time devices for automatically correcting the time scale to an hour inclusive with the help of time-sensitive information check signals and is an improvement to the device described in the author. N 700854. The goal is to automate the session of the correction of the time scale by the signals of the exact time, which are transmitted over the sound broadcasting network. The input of the AND 16 circuit receives a correction impulse equal in duration to the sixth signal of the enhanced informativity time check (PFR), to the other input of which pulses are received from the generator 13. A pulse is applied to the third input of the AND 16 circuit allowing the impulse to pass to the input of the imager 17 13 from the trigger output 12, if the duration of the sixth signal PvPI more than 100 ms. The input of the memory circuit 18 receives pulses with a period of 20 ms, the number of which corresponds to the value of the currently transmitted hour. 3 il.

Description

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The invention relates to instrumentation, can be used in time devices for automatically correcting the time scale to an hour inclusive with the help of time-checking signals of increased informativity and is an improvement of the device according to the author. No. 700854.

The aim of the invention is to automate the session of the correction of the time scale by the signals of the exact time, which are transmitted over the sound broadcasting network.

Figure 1 shows the structure of the signals of the new form; Fig.2 is a structural diagram of the selector; in fig. 3 is a schematic diagram of blocks of additional time signals added to the selector.

The selector consists of amplifier - limiter 1, driver 2 pulses, trigger 3 with a counting input, differentiating circuit 4, trigger 5 with separate inputs, circuit 6 delays adder 7 modulo two, integrator 8, differentiating circuit 9, accumulator 10, threshold device 11 and additionally introduced into the circuit of the trigger 12 with separate inputs, a generator of 13 pulses, a two-input circuit AND 14, a delay generator 15, a three-input circuit 16, a cycle generator 17, a memory block 18 and a differentiating circuit 19

Limiting amplifier 1, pulse generator 2, trigger 3, differentiating circuit 4, trigger 5, delay circuit 6, the output of which is connected to the second input of the trigger 5, the first output of which is connected to the second input of the sum of 7, the first input of which is connected to trigger output 3, and the output with the second input of the integrator 8, the first input of which is connected to the output of the impulse generator 2., and the output connected to the input of the differentiating circuit 9, the output of which is connected to the input of the storage device 10, the output of which is connected to the input threshold New device 1 1.

The output of the generator 13 is connected to the inputs of the circuits And 14 and 16. The second input of the circuit And 14 is connected to the output of the trigger 12. To the output of the circuit And 14 is connected to the driver 15 delay, and to the output of the driver 15 one of two

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The inputs are connected to a trigger 12. The output of the exact time signal selector (threshold device 11) is connected to a circuit 16 and a differentiation circuit 19, the output of which is connected to the second input of the trigger 12, to the driver 15 of the delay and cycle 17, as well as to the circuit 18 of the value memory hours The second output of the trigger 12 is connected to the third input of the AND 16 circuit. The output of the AND 16 circuit is connected to the cycle generator 17, the output of which is connected to the circuit, 18 hour value memory, which has parallel information outputs of the hour values.

Blocks 12 - 19 work as follows.

A correction impulse equal in duration to the sixth signal of the enhanced informativity time check (PSTI) (FIG. I) is fed to one of the three inputs of the AND-HI circuit 16, thereby preparing a 1 kHz pulse sequence through this circuit. At the same time, on the leading edge of the correction pulse, differentiating circuit 19, consisting of capacitor C1, register RI and diode VD, provides a pulse that goes to one of the setup inputs (pin 4) of trigger 12 and writes to trigger 1, and also sets the initial (zero) position of the formers 15 and 17 and the memory circuit 18. From the direct output of flip-flop 12 (pin 5), permission is given to passing 14 pulses through the AND-HE circuit with a 1 kHz following frequency, generated by a pulse generator 13. At the same time, the inverse output of the trigger 12 (pin 6) is prohibited from passing a 1kHz pulse sequence through the AND-HI circuit 16 (pin 1). The generator 13 is assembled according to a scheme of three series-connected HI-33, 20 and 21 circuits, as well as a resistor R2 and capacitor C2. The 1 kHz pulse sequence from the output of the circuit 21 is fed through the AND-NE 14 circuit to the input of the delay generator 15 for 100 ms5 made of two serially connected counters-dividers 22 and 23 by ten.

Thus, at the output of the imaging unit 15 (circuit 23, contact 12), a pulse is formed, the beginning of which is separated from the beginning of the correction pulse (the sixth PFR signal) by 4,100 ms. With this pulse from the output of circuit 23 (pin 12), trigger 12 (contact I) is set to the initial (zero) position. Simultaneously from the inverted output of the trigger 12 (pin 6), permission is given to the AND-16 circuit (pin I) for passing through this circuit (pin 13) of the 1 kHz pulse sequence from the generator output 13 pulses (circuit 21, pin 11) under the condition that it arrives the output of the threshold device 11 to the input of the NAND 16 circuit (pin 2) of the correction pulse (the sixth PFR signal) of more than 100 ms (figure 1). When this condition is fulfilled, the 1 kHz pulse sequence from the output of the NAND 16 circuit (pin 12) is fed to the input of the shaper 17 of a 20 ms cycle, which is a counter (20) and is made of a series-connected inverter 24, trigger 25 and counter a- divides ate 26 into ten. Pulses with a follow-up period of 20 ms, the number of which corresponds to the value of the currently transmitted hour, arrive at the input of the generator 17 of the cycle for 20 ms (circuit 26, pin 12) to the input of circuit 18 of the hour value memory.

The memory circuit consists of two series-connected dividers counters for ten (circuit 27) and three (circuit 28), which with the OR-HE circuits 29 and 32 and inverters 30 and 31 form a counter for 24, Circuits 29-32 are needed to form a zero counter circuit for 24 (circuits 27 and 28) with a pulse from the output of the differentiating circuit 19 and the reverse

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ten (circuit 27) and three (circuit 28). Thus, the current hour information is recorded in the counter at 24 (circuits 27-32) and stored there until the next time scale correction session. At the same time, the stored information can be accessed through the parallel outputs of counters 27 and 28.

The hour information is stored in the memory circuit 18 and can be read from the parallel information outputs of the hour values in the binary-decimal 15 code 8-4-2-1 for setting and checking the hour values.

formula of invention

Time signal selector auth.St. No. 700854, characterized in that, for the purpose of automating a time scale correction session using accurate time signals, it is provided with serially connected by a pulse generator, a first AND circuit, a delay generator, a trigger, a second AND circuit, a loop generator, a memory circuit and a differentiating circuit The input of which is connected to the output of the signal selector. The exact time and the second input of the second AND circuit, and the output to the second input of the trigger and the zeroing inputs of the delay generator, the cycle former and the memory circuit, which has a parallel nye data outputs values of h, the pulse generator output is connected to the third input of the second AND gate and the second flip-flop output - to a second input of the first AND gate,

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Claims (1)

Claim 70 Time signal selector, auth.St. No. 700854, characterized in that, in order to automate the time scale correction session using accurate time signals, it is equipped with a pulse generator sequentially connected, a first And circuit, a Delay Shaper, a trigger, a second And circuit, a shaper of a memory, a memory circuit and a differentiating circuit The input of which is connected to the output of the signal selector of the current time and the second input of the second AND circuit, and the output to the second input of the trigger and the inputs of the null of the delay driver, the cycle former and the memory circuit that has a parallel the informational outputs of the hour, the output of the pulse generator is connected to the third 40 input of the second circuit And, and the second output of the trigger - with the second input of the first circuit I. / ϊόνΟΛΰ СЛСОО / УцРго у ос О 53c OOS 1 569797