SU1661966A1 - Controlled digital delay line - Google Patents

Abstract

The invention relates to computing and measuring technology and can be used in automation devices. The purpose of the invention is to enhance the functionality by dynamically varying the delay and a predetermined change in the duration of the output signal. This is achieved by introducing into the device the element AND - NOT 6, register 7, bus 10 of the initial installation with the corresponding connections. The digital adjustable delay line also contains a clock pulse generator 1, the first element AND 2, the first counter 3, the second element AND 4, the second counter 5, the code bus 8, the input bus 9 and the output bus 11. In the proposed device, it is possible to form an output pulse with different delay times by dynamically asynchronous changing the delay code on the code buses 8. In addition, when the duration of the input pulse is less than the programmable delay time, it is possible to specify the change in litness of the output pulses T _out = T _in / M, where T _out , T _in are, respectively, the duration of the output and input pulses

M is a constant determining the change in the frequency of the clock generator as the control action changes at its input. 2 Il.

Description

the input of which is connected to the output of the loan of the second counter 5 and the output bus 11, and the output is connected to the input of the register entry 7, the information inputs of which are connected to the code buses 8 and the information inputs of the second counter 5, and the outputs to the information inputs of the first counter 3, the output of the loan which is connected to the control input of the second counter 5, the loan output of which is connected to the control input of the generator 1. On the code bus 8 receives codes defining the shift of the output pulse relative to the input, on the input bus 9 - input signal (pulse or video signal); on the initial installation bus 10, the pulse generated by the circuit triggered when the power is turned on (not shown in Figure 1).

The device works as follows.

When the power is turned on, a single pulse of negative polarity appears on bus 10 of the initial installation (Fig. 2b). When the power is turned on, the states of the counters 3 and 5 can be any, and logical or zero levels appear at their loan outputs units. If at the output of the loan of the second counter 5 a logical zero level (FIG. 2k), then the leading (negative) front edge of the initial setup (FIG. 2b) will reset the first counter 3, and the logical zero level will appear at its loan output (FIG. 2b), which prohibits the passage of clock pulses through the element 2 (fig.2zh) and writes to the counter 5 the code delay code 8. 8. at the output of the loan counter 5, the level of the logical unit (fig.2k). At the same time, the level of the logical unit at the output of the AND-HE element 6 does not change (Fig. 2d), since at its first input the level of the logical zero of the initial installation pulse (Fig. 2b). The level of the logical unit at the output of the loan of the counter 5 permits the passage through the AND element of 4 clock pulses to the subtractive counting input of the counter 5 (Fig. 2 and) without changing its state, since at a zero signal at the control input the counter is in the recording mode, in which the work of the counter on the counting inputs is blocked.

If at the exit of the loan of the second counter 5 with the arrival of the initial setup pulse there was a logical unit level (FIG. 2k, dashed line), then the initial setup pulse, recording the delay code from the code buses 8, does not change this level, and the output element and NOT 6

the level of the logical unit appears (Figure 2d, dashed line).

With the arrival of the rear (positive) pulse edge of the initial installation

(fig.2b) a negative differential appears on the output of the element IS-NE 6 (fig.2g), which writes to the register 7 the code of the delay from the code lines 8, sets the device to its initial state before the appearance of a pulse

0 on the input bus 9. Thus, when the power is turned on by the front (negative) pulse edge of the initial installation from the bus 10, the delay code is written to counter 5, and the back (positive) front to register 7. At the output of the counter 5, it sets the level of the logical unit (fig.2k).

The generator 1 generates clock pulses with a period r0 (figv). When coming

0 of the input pulse (FIG. 2c) by the level of logical zero, the counter 3 is set to the state corresponding to the delay code at the outputs of register 7. At the same time, the level of the logical unit (FIG. 2h) allowing the passage of clock pulses from the generator 1 to subtracting the counting input of counter 3 through the element 2, as well as the recalculation of the pulses from the clock generator 1 by the counter 5. Since the counter 5 is in the state corresponding to some delay code Ki, then through the delay time ts Ki TO relative to its input signal in the front he ustanovits nil;

5 at its output by Wits logical level zero (Fig.2k), which, entering the input element And 4, prohibits the passage through it of pulses from generator 1 to the subtracting counting input of this counter 5

0 (Fig.2i) / 0 at the same time the logic zero level at the loan output of the counter 5 sets the level of the logical unit at the output of the AND-HE element 6 (Fig.2g) and, arriving at the control input of the generator 1, changes 5 times the frequency of clock pulses . During the entire pulse time of the input signal (Fig. 2c), the counter 3 is in the state Ki, but after it ends, the control input of the counter 3 appears

0 logical units enabling clock recalculation.

There are two possible occurrences of the output pulse:

5 1) output pulse by wils at the end of the input pulse (t3 tBx);

2) the output pulse is wils at the time when the input pulse has not finished (t3 tux).

In the first case, the level of the logical unit at the control input of counter 3 permits the recalculation of clock pulses following with a period T0, and after the delay time t3 Kir0 relative to the leading edge of the input signal, the recalculation of clock pulses following with a period of T0 / t (Fig. 2g). If the duration of the input signal is I t (where l Ki), then from the time the logical unit level appears at the control input of counter 3 to the time the logical zero level appears at the output of counter 5, the number KI -I is subtracted from 3 the output pulse of the counter 5, the state of counter 3 corresponds to code I. Then, after time I r0 / m relative to the leading edge of the pulse from the output of the counter 5, the counter 3 is set to zero, the logic zero level at its loan output prohibits the passage of clock pulses through the element 2 (fig.2g) and writes a delay code into counter 5, as a result of which a logic unit level appears on its output (fig.2k), which forms the falling edge of the output pulse of the delay line, returns to its original value oscillator clock period of generator 1 (fig.2e), allows clock pulses with period r0 through element 4 to the subtracting counting input of counter 5 (fig.2i) and causes the logic zero to appear at the output of element AND-6 6 (fig. 2d), which records the code delay with code shi n 8 in register 7.

Thus, the device returns to its original state, the delay code is simultaneously recorded in counter 5 and register 7, a pulse is generated at the output of the device, which is delayed relative to the input one at time ta - Ki T0 and equal in duration tBx / in. An asynchronous change of the delay code (in Fig. 2d it is conditionally shown its change - reduction) does not affect the operation of the device, since the delay code is recorded simultaneously in counter 5 by a negative pulse from the output of the counter 3 borrowing (Fig. 2h) and in register 7 ( Fig. 2e shows a conventionally negative edge of the pulse from the output of the element IS-NE 6 (Fig. 2d), the state of which does not affect the asynchronous change of the delay code.

In the second case, the appearance of the output pulse. Through the time Ka TO (K2t0 tBx) from the beginning of the input pulse, the output of the counter 5 borrows a logical zero level (Fig. 2k), which, on entering the input of the And 4 element, prohibits the passage through it impulses from generator 1 to the subtracting counting input of this counter 5 (fig.2i), sets the level of logical 5 units at the output of the NAND element (fig.2g) and changes the frequency of the clock pulses of generator 1 by m times (fig.2a).

Counter 3 is blocked by the logical zero level of the input pulse at its control input (Fig. 2b), and counter 5 is kept in the zero state by the absence of clock pulses from the output of the And 4 element at its subtracting counting input (Fig. 2i).

5 At the time of the appearance of the logical level

the input pulse unit at the control input of the counter 3 its state corresponds to the delay code K2 and after a time of "2 T0 / t from the moment the level of the logical unit appears at its control input, at its output of the loan, the level zero appears, which prohibits the passage of clock pulses through the element And 2 (Fig.2zh) and writes to

5, the counter 5, the delay code, as a result of which a logic unit level appears on its loan output (FIG. 2k), which forms the falling edge of the output pulse of the delay line, returns to its original value

0 the period of the clock pulses of the generator 1 (fig. 2a), allows the arrival of clock pulses with a period r0 through the element 4 and into the subtracting counting input of the counter 5 (fig. 2i) and causes the appearance at the output

5 of an AND-NE element 6 is a logic zero level (FIG. 2d), which writes the delay code from the code buses 8 to register 7 (FIG. 2e). The device returns to its original state, a pulse is generated at the device output,

0 delayed relative to the input time Tz K2 t0 and equal in duration tux-K2G0 (1 - 1 / pp).

Thus, the device has enhanced functionality.

5 in comparison with the known and capable of performing the following functions:

1. Formation of an output pulse with a controlled delay of K for a period of clock pulses relative to the input signal and a duration equal to the duration of the input signal (for m 1).

2. Formation of an output pulse with a controlled delay of K periods of clock pulses relative to the input signal and a controlled (specified) duration equal to m, output tex / m, while the duration of the input pulse is less than the delay time

3. Formation of an output pulse with a controlled delay of K periods of clock pulses relative to the input signal and a controlled (predetermined) duration equal to 1out t.Vx- Kt (1-1 / t), with a duration of the input pulse greater than the delay time.

A. Generating an output pulse with different delay times by dynamically asynchronously changing the delay code on the code buses 8.

5. The formation of the inverse value of the output delayed pulse, which can be removed from the output of the element AND-NOT 6.

Claims (1)

Invention Formula A digitally adjustable delay line containing the first and second elements And, the outputs of which are connected to the subtractive counting inputs of the first and second counters, respectively, the first inputs of the first and second elements And connected to the output of the clock generator, the second inputs connected to the outputs of the loan the first and second counters, respectively, the control input of the first counter and the output of the second counter, are connected respectively to the input and output buses, the control input of the second counter is connected to the output of the first counter, and the information inputs of the second counter are connected to the code buses, that, in order to expand fields of application due to the possibility of dynamically varying the delay and a predetermined change in the duration of the output pulse, the register, the NAND element and the initial bus are entered into it installation, connected to the installation input of the first counter and the first input of the NAND element, the second input of which is connected to the loan output of the second counter and the generator control input, the output of the element I-NOT is connected to the register entry input, the information inputs of which are connected to the code bus, and the outputs - to the information inputs of the first counter. Lls 1 l-j Jl P P DLL PK J ± 1 RPPPPPPPP JUUlJnJL Kjto 4x / m i ft PI u JLJUULJUUIJI kgG0 6x- “2ndO- / p) Fie.2