JPS5740965A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS5740965A
JPS5740965A JP11739480A JP11739480A JPS5740965A JP S5740965 A JPS5740965 A JP S5740965A JP 11739480 A JP11739480 A JP 11739480A JP 11739480 A JP11739480 A JP 11739480A JP S5740965 A JPS5740965 A JP S5740965A
Authority
JP
Japan
Prior art keywords
dam
circuit board
integrated circuit
circuit device
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11739480A
Other languages
Japanese (ja)
Inventor
Toshio Hiroe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11739480A priority Critical patent/JPS5740965A/en
Publication of JPS5740965A publication Critical patent/JPS5740965A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive

Abstract

PURPOSE:To prevent a circuit board from displacement and an adhesive from overflowing, by providing a dam along the rim of a circuit board on which a heat sink is mounted. CONSTITUTION:A dam 13 is provided along the rim of a circuit board 1 on which a heat sink 11 is mounted. A groove 13 is provided along the inner side of the dam 12. As a result, an adhesive 13 does not overflow before hardening. As the circuit board 1 is fastened by the dam 12, mislocation does not occur. Therefore, mislocation and adhesive overflow can be prevented and yield can be improved. Said dam and groove can be pressed in process. An electronic part is shown as 2 in Figure.
JP11739480A 1980-08-26 1980-08-26 Hybrid integrated circuit device Pending JPS5740965A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11739480A JPS5740965A (en) 1980-08-26 1980-08-26 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11739480A JPS5740965A (en) 1980-08-26 1980-08-26 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5740965A true JPS5740965A (en) 1982-03-06

Family

ID=14710557

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11739480A Pending JPS5740965A (en) 1980-08-26 1980-08-26 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5740965A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01205032A (en) * 1988-02-09 1989-08-17 Nippon Steel Corp Manufacture of high-strength electric resistance welded tube for automobile use
JPH01130552U (en) * 1988-02-29 1989-09-05
US5150197A (en) * 1989-10-05 1992-09-22 Digital Equipment Corporation Die attach structure and method
EP0829097A4 (en) * 1995-05-26 1999-04-14 Hestia Technologies Inc Method of transfer molding electronic packages and packages produced thereby
KR100220492B1 (en) * 1996-12-06 1999-09-15 윤종용 Clip lead package
KR100386635B1 (en) * 2000-12-29 2003-06-02 앰코 테크놀로지 코리아 주식회사 Method for manufacturing substrate in semiconductor package
JP2005005671A (en) * 2003-05-19 2005-01-06 Denso Corp Heat dissipation structure of electronic component
EP1898465A2 (en) 2006-09-11 2008-03-12 Hitachi, Ltd. Power semiconductor module
JP2009164508A (en) * 2008-01-10 2009-07-23 Nissan Motor Co Ltd Method of fabricating bonding member, and bonding structure

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01205032A (en) * 1988-02-09 1989-08-17 Nippon Steel Corp Manufacture of high-strength electric resistance welded tube for automobile use
JPH01130552U (en) * 1988-02-29 1989-09-05
US5150197A (en) * 1989-10-05 1992-09-22 Digital Equipment Corporation Die attach structure and method
EP0829097A4 (en) * 1995-05-26 1999-04-14 Hestia Technologies Inc Method of transfer molding electronic packages and packages produced thereby
KR100220492B1 (en) * 1996-12-06 1999-09-15 윤종용 Clip lead package
KR100386635B1 (en) * 2000-12-29 2003-06-02 앰코 테크놀로지 코리아 주식회사 Method for manufacturing substrate in semiconductor package
JP2005005671A (en) * 2003-05-19 2005-01-06 Denso Corp Heat dissipation structure of electronic component
EP1898465A2 (en) 2006-09-11 2008-03-12 Hitachi, Ltd. Power semiconductor module
EP1898465A3 (en) * 2006-09-11 2011-05-04 Hitachi, Ltd. Power semiconductor module
JP2009164508A (en) * 2008-01-10 2009-07-23 Nissan Motor Co Ltd Method of fabricating bonding member, and bonding structure

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