JPS5764953A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5764953A
JPS5764953A JP55140526A JP14052680A JPS5764953A JP S5764953 A JPS5764953 A JP S5764953A JP 55140526 A JP55140526 A JP 55140526A JP 14052680 A JP14052680 A JP 14052680A JP S5764953 A JPS5764953 A JP S5764953A
Authority
JP
Japan
Prior art keywords
metalized
case
cover
pattern
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55140526A
Other languages
Japanese (ja)
Inventor
Hiromi Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP55140526A priority Critical patent/JPS5764953A/en
Publication of JPS5764953A publication Critical patent/JPS5764953A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/647—Resistive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce the mounting area of a semiconductor device by a method wherein metalized parts are provided in a cover of sealing case and accessories are fixed thereto, and the metalized parts are connected to the outside lead of the case. CONSTITUTION:The metalized pattern 15 is provided in the case 11, and is connected to the metalized pattern 14 for leading out to an outside electrode. Afrer a semiconductor chip 12 is assembled therein and connection 13 is finished, when the cover 18 is sealed with glass 21, a resistor 19 processed on the cover is connected to the outside lead 22 through the metalized pattern 17 in a through-hole 16 from the metalized pattern 15. When the resistor 19, etc., are accommodated in the case, the mounting area on the printed wiring substrate can be reduced remarkably.
JP55140526A 1980-10-09 1980-10-09 Semiconductor device Pending JPS5764953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55140526A JPS5764953A (en) 1980-10-09 1980-10-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55140526A JPS5764953A (en) 1980-10-09 1980-10-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5764953A true JPS5764953A (en) 1982-04-20

Family

ID=15270710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55140526A Pending JPS5764953A (en) 1980-10-09 1980-10-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5764953A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594061A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semiconductor device
JPS593544U (en) * 1982-06-30 1984-01-11 富士通株式会社 Packages for semiconductor devices
JPS59143355A (en) * 1983-02-04 1984-08-16 Nec Corp Semiconductor integrated circuit device
JPS59149645U (en) * 1983-03-22 1984-10-06 京セラ株式会社 semiconductor package
US4539622A (en) * 1981-06-25 1985-09-03 Fujitsu Limited Hybrid integrated circuit device
JPS60171754A (en) * 1984-02-17 1985-09-05 Sumitomo Electric Ind Ltd Semiconductor chip carrier provided with circuit element
JPS6139551A (en) * 1984-05-25 1986-02-25 コンパニイ・ダンフオルマテイク・ミリテ−ル・スパテイアル・エ・アエロノ−テイク Potential distributing device and case for electronic constituent containing same device
JPS6217153U (en) * 1985-07-15 1987-02-02
JPH0348234U (en) * 1989-09-18 1991-05-08
EP1746866A1 (en) * 2005-07-19 2007-01-24 Samsung Electronics Co., Ltd. Packaging chip having inductor therein

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4539622A (en) * 1981-06-25 1985-09-03 Fujitsu Limited Hybrid integrated circuit device
JPS635232Y2 (en) * 1982-06-30 1988-02-12
JPS593544U (en) * 1982-06-30 1984-01-11 富士通株式会社 Packages for semiconductor devices
JPS594061A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semiconductor device
JPS59143355A (en) * 1983-02-04 1984-08-16 Nec Corp Semiconductor integrated circuit device
JPS59149645U (en) * 1983-03-22 1984-10-06 京セラ株式会社 semiconductor package
JPS60171754A (en) * 1984-02-17 1985-09-05 Sumitomo Electric Ind Ltd Semiconductor chip carrier provided with circuit element
JPS6139551A (en) * 1984-05-25 1986-02-25 コンパニイ・ダンフオルマテイク・ミリテ−ル・スパテイアル・エ・アエロノ−テイク Potential distributing device and case for electronic constituent containing same device
JPS6217153U (en) * 1985-07-15 1987-02-02
JPH0514517Y2 (en) * 1985-07-15 1993-04-19
JPH0348234U (en) * 1989-09-18 1991-05-08
EP1746866A1 (en) * 2005-07-19 2007-01-24 Samsung Electronics Co., Ltd. Packaging chip having inductor therein
US7541662B2 (en) 2005-07-19 2009-06-02 Samsung Electronics Co., Ltd. Packaging chip having inductor therein

Similar Documents

Publication Publication Date Title
JPS56105643A (en) Method of assembling container with semiconductor device
DE2961000D1 (en) Electronic circuit assembly for testing module interconnections
JPS6428930A (en) Semiconductor device
EP0081135A3 (en) Substrate for mounting integrated circuit chips
JPS5764953A (en) Semiconductor device
DE3165480D1 (en) Method of sealing an electronic module
CH623452GA3 (en)
DE3268393D1 (en) Device and method for packaging electronic devices
DE3176292D1 (en) Substrate and integrated circuit module with this substrate
JPS6216553A (en) Power semiconductor device with incorporated control circuit
JPS5740965A (en) Hybrid integrated circuit device
JPS53112061A (en) Wiring substrate of semiconductor chip
JPS5558557A (en) Resin mold type electronic component and lead frame used therefor
GB2056772B (en) Integrated circuit package and module
GB2037128B (en) Electronic telephone on a chip
JPS5720500A (en) Electronic circuit module
JPS5769762A (en) Sealing method of hybrid integrated circuit
JPS6489356A (en) Hybrid integrated circuit
JPS55123151A (en) Integrated circuit device
GB2069756B (en) Arrangement of diodes integrated on an insulating substrate
JPS57187955A (en) Sealing structure of semiconductor element
JPS55138240A (en) Manufacture of semiconductor device
JPS5521110A (en) Package for accommodating semiconductor parts
JPS52116073A (en) Hermetic structure in which integrated circuit element is sealed up ai rtightly
JPS5760845A (en) Manufacture of hybrid ic