JPS55138240A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55138240A
JPS55138240A JP4403179A JP4403179A JPS55138240A JP S55138240 A JPS55138240 A JP S55138240A JP 4403179 A JP4403179 A JP 4403179A JP 4403179 A JP4403179 A JP 4403179A JP S55138240 A JPS55138240 A JP S55138240A
Authority
JP
Japan
Prior art keywords
resin
substrate
wiring
chip
printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4403179A
Other languages
Japanese (ja)
Inventor
Tsuneo Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP4403179A priority Critical patent/JPS55138240A/en
Publication of JPS55138240A publication Critical patent/JPS55138240A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Abstract

PURPOSE:To obtain a thin resin seal by a method wherein, when a semiconductor chip is sealed with resin, the chip is mounted on a printed-wiring substrate, specified wiring connections are made, a printed frame having a property of repelling resin is provided on the substrate surrounding the chip, resin is dripped inside this, and it is left as it is. CONSTITUTION:A semiconductor chip 12 is fixed on a printed-wiring substrate 11, on which specified wiring is provided. This electrode is connected to the wiring on the substrate 11 by using fine wire 13. Next, silicone resin 17, having a property of repelling sealing resin 16 is coated on the substrate 11 surrounding the chip 12, and a fixed amount of resin 16 is dripped inside this. Subsequently, this is left at a proper temperature, the resin 16 is cured, and thereby a resin layer with smooth surface is obtained. By this, the sealing resin layer can be made thin, suitable for use in the hybrid circuit of the watch.
JP4403179A 1979-04-11 1979-04-11 Manufacture of semiconductor device Pending JPS55138240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4403179A JPS55138240A (en) 1979-04-11 1979-04-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4403179A JPS55138240A (en) 1979-04-11 1979-04-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55138240A true JPS55138240A (en) 1980-10-28

Family

ID=12680263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4403179A Pending JPS55138240A (en) 1979-04-11 1979-04-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55138240A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02100334A (en) * 1989-04-26 1990-04-12 Seikosha Co Ltd Potting of circuit element
JPH02100333A (en) * 1989-02-15 1990-04-12 Seikosha Co Ltd Potting equipment
JPH0964077A (en) * 1995-08-29 1997-03-07 Nippon Retsuku Kk Method of manufacturing electronic component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02100333A (en) * 1989-02-15 1990-04-12 Seikosha Co Ltd Potting equipment
JPH02100334A (en) * 1989-04-26 1990-04-12 Seikosha Co Ltd Potting of circuit element
JPH0964077A (en) * 1995-08-29 1997-03-07 Nippon Retsuku Kk Method of manufacturing electronic component
JP2934174B2 (en) * 1995-08-29 1999-08-16 日本レック株式会社 Electronic component manufacturing method

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