JPS5739564A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5739564A
JPS5739564A JP55115025A JP11502580A JPS5739564A JP S5739564 A JPS5739564 A JP S5739564A JP 55115025 A JP55115025 A JP 55115025A JP 11502580 A JP11502580 A JP 11502580A JP S5739564 A JPS5739564 A JP S5739564A
Authority
JP
Japan
Prior art keywords
silicon
film
region
oxidized
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55115025A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP55115025A priority Critical patent/JPS5739564A/en
Publication of JPS5739564A publication Critical patent/JPS5739564A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To highly integrate an integrated circuit by arraying a load resistance region in a longitudinal direction vertical to the plane of a substrate. CONSTITUTION:A field region 13 made of a relatively thick oxidized silicon film or the like is formed on a silicon substrate 10, and an MOS transistor having a source diffused region 11, a drain diffused region 12, a gate insulated film 14 and a gate 15 is formed on the element forming region surrounded by the field. A silicon oxidized film 17 is formed on a polycrystalline silicon wiring layer. Ions of element, e.g., Cr, Si, Ar, C or the like are injected on a dielectric unit of thin silicon oxidized film, silicon nitrided film, etc. having 100Angstrom or less thick, or dielectric film of silicon oxidized film or the like to form a layer forming a load resistance region 16, which is in turn formed on a source region through a contacting hole. Thereafter, an aluminum wiring layer 18 is formed.
JP55115025A 1980-08-21 1980-08-21 Semiconductor integrated circuit device Pending JPS5739564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55115025A JPS5739564A (en) 1980-08-21 1980-08-21 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55115025A JPS5739564A (en) 1980-08-21 1980-08-21 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5739564A true JPS5739564A (en) 1982-03-04

Family

ID=14652356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55115025A Pending JPS5739564A (en) 1980-08-21 1980-08-21 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5739564A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4318334Y1 (en) * 1964-11-16 1968-07-30
JPS49112326A (en) * 1973-02-16 1974-10-25

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4318334Y1 (en) * 1964-11-16 1968-07-30
JPS49112326A (en) * 1973-02-16 1974-10-25

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