JPS5732161A - Modulation system for digital signal - Google Patents

Modulation system for digital signal

Info

Publication number
JPS5732161A
JPS5732161A JP10676680A JP10676680A JPS5732161A JP S5732161 A JPS5732161 A JP S5732161A JP 10676680 A JP10676680 A JP 10676680A JP 10676680 A JP10676680 A JP 10676680A JP S5732161 A JPS5732161 A JP S5732161A
Authority
JP
Japan
Prior art keywords
bit
pulse
pattern
frames
erasure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10676680A
Other languages
Japanese (ja)
Inventor
Norio Seki
Haruo Sakaguchi
Shu Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KDDI Corp
Original Assignee
Kokusai Denshin Denwa KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Denshin Denwa KK filed Critical Kokusai Denshin Denwa KK
Priority to JP10676680A priority Critical patent/JPS5732161A/en
Publication of JPS5732161A publication Critical patent/JPS5732161A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/40—Monitoring; Testing of relay systems

Abstract

PURPOSE:To improve the reliability of remote repeater control without using any interposing line, by inserting one-bit signals between specific frames among (n) frames of a synchronous (m)-bit pattern at a constant interrupt insertion rate. CONSTITUTION:A pulse generated when a word detector 1 in a pseudo-random signal generator PRG detects a preset specific bit pattern in a shift register S1 is applied to a clock erasure pulse generating circuit CAP and an N-bit counter 4 through a one-bit delay element b0. The circuit CAP generates clock erasure pulses P2 at (m)-bit intervals; when the pulse P2 is a ''1'', a one-bit signal having the same value with the final bit of the (m)-bit pattern is applied to the output signal Q of the generator PRG and when the pulse P2 is a ''0'', a pattern with a period of (m) bits is outputted.
JP10676680A 1980-08-05 1980-08-05 Modulation system for digital signal Pending JPS5732161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10676680A JPS5732161A (en) 1980-08-05 1980-08-05 Modulation system for digital signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10676680A JPS5732161A (en) 1980-08-05 1980-08-05 Modulation system for digital signal

Publications (1)

Publication Number Publication Date
JPS5732161A true JPS5732161A (en) 1982-02-20

Family

ID=14442020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10676680A Pending JPS5732161A (en) 1980-08-05 1980-08-05 Modulation system for digital signal

Country Status (1)

Country Link
JP (1) JPS5732161A (en)

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