SU1661744A1 - Special shape signal generator - Google Patents

Abstract

This invention relates to digital signal conditioning devices. The purpose of the invention is the expansion of the class of tasks due to the ability to form signals of various shapes and control the duty cycle of the output signal. The generator contains a generator of 1 clock pulses, a switch 2, a counter 3, an amplitude memory block 4, a digital-to-analog converter 7, a register 6, a signal code sensor 5, a duty ratio code sensor 9, a reversing counter 8, a T-flip-flop 10, an AND-11 element This goal is achieved by the introduction of register 6, reversible counter 8, T-flip-flop 10, AND-NOT element 11. 2 Il.

Description

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The invention relates to digital signal generation devices and can be used in radio measuring technology as a source of signals of complex shape.

The aim of the invention is to expand the class of tasks due to the ability to generate signals of various shapes and adjust the output signal's duty cycle.

FIG. 1 shows the structure-Ya diagram of a generator of signals of a special form in FIG. 2 — timing diagrams of the generator.

A special waveform generator (Fig. 1) contains a clock pulse generator 1, a switch 2, a counter 3, an amplitude memory block 4, a signal code sensor 5, a register 6, a D / A converter 7, a reversing counter 8, a Bore curve sensor 9 T-trigger 10, AND-NOT element 11.

The generator works as follows.

From the output of the clock generator 1 or the clock input of the device, the pulses through the switch 2 are fed to the input of counter 3 and the input of the record of register 6, From the output of counter 3, a sequence of binary codes. It enters the lower address inputs of the amplitude memory 4. Unit 4 converts the phase code coming from Counter 3 into an amplitude code in accordance with the signals sampled in the ROM area selected by the code received from sensor 5 of the Signal Code. From the output of unit 4, the amplitude code is entered into register 6 by the Impulse incoming to the register entry 6 with switch 2.

i. With the transfer output of the counter 3, the pulses arrive at the subtracting input of the reversible counter 8. As soon as the number of pulses from the transfer output of counter 3 coincides with the number determined by sensor code 9 of the duty ratio, a transfer pulse is generated at the output of the reversible counter the code of the duty ratio is again entered from the sensor 9 of the code. the duty cycle in the reversible counter and the T-flip-flop 10 is set to the state of the logical unit at the forward output Q. The signal of the logical unit from the T-flip-flop output 10 is fed to the reset input of the register 6 and,

thus, it enables the entry of information into register 6. In addition, the signal of the logical unit arrives at the second input of the NAND element 11 and allows the transfer of the transfer pulse from the output of counter 3, which returns the T-trigger to the initial state,

Thus, register 6 is allowed to enter information in one period and it is prohibited to enter information in all other periods in accordance with

5 code from the output of the sensor 9 code of duty ratio.

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As an example, figure 2 shows the formation of a trapezoidal signal.

The clock frequency signal of FIG. 2a goes through a switch 2 to counter 3, where it is converted into code 5 of the phase of FIG. 26 and the transfer signal of FIG. The phase code of FIG. 36 is converted by block 4 into an amplitude code, which takes an instantaneous amplitude value of FIG. 2g at the output of the digital-to-analog converter 7. The transfer signal of the counter 3 of FIG. 2b is fed to the subtracting input of the reversible counter 8, into which the transfer signal of the counter 3 And if at all outputs the value of logical zero forms its transfer signal fig.2d. The transfer signal of the reversible counter (FIG. 2d) transfers the T-flip-flop 10 to the state of the logical unit at the direct Q output 0. (FIG. 2e) and enters into the reversible counter 8 the duty ratio from the duty ratio code sensor. The signal of the logical unit from the output T-flip-flop 10 (FIG. 2e) is fed to the input of the register-5 pa 6 and allows the passage of information from block 4 to the digital-to-analog converter (Fig. 2h). At the same time, the signal of the logical unit (FIG. 2e) is fed to the second input of the AND-HE element 11 and “thus, time

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five

solves the passage of the transfer pulse of the counter 3 to the counting input of the T-flip-flop 10 (FIG. 2g), which translates the T-flip-flop to the logical zero state at the direct output Q (Fig. 2e). When a logical zero appears at the output of the T-flip-flop 10, the register 6 does not pass information to the digital-to-analogue converter 7 (Fig. 2h).

Claims (1)

Invention Formula A special-shaped signal generator containing a counter, an amplitude memory block, a register, an NAND element, the generator synchronization clock being connected to the counter's counting input, the information output of which is connected to the lower group of bits of the address input of the amplitude memory block, that, in order to expand the class of tasks due to the ability to form signals of various shapes and control the duty cycle of the output signal, a register, a reversible counter, a T-flip-flop, an NAND element, and an output block the memory of amplitudes is connected to the information input of the register, the input is the syn component S. Kurosh Editor N. Lazorenko Tehred m.Didyk The jg j $ 20 synchronization of which is connected to the synchronization input of the generator, the transfer output of the counter is connected to the subtracting input of the reversible counter and the first input of the NAND element, the second input of which is the register write enable input and the output of the generator maintenance output connected to the T-trigger output, counting input and the reset input of which is connected respectively to the transfer output of the reversible counter and the output of the NAND element, the inputs of the function selection and the duty cycle of the generator are connected respectively to the older group of bits dresnogo input memory block the input amplitudes and receiving parallel information down counter, respectively, the register output is connected to the generator output. FIG. 2 Proofreader L. Patay