SU1538236A1 - Device for shaping time intervals - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital systems to form pulse sequences defining time intervals. The purpose of the invention — improving reliability — is achieved by gating the address codes driver. The device for generating time slots comprises a clock pulse generator 1, a control pulse generator 2, a pulse counter 3, a persistent memory 4, an address code generator 5, an OR 7 multi-input element, a delay element 8, and a pulse generator 9. In this device, the delay value of the output pulse is determined by the delay from the output of the generator 1 to the output of the first discharge of counter 3, which allows the element base to be used with low speed. 1 il.

Description

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The invention relates to a pulse technique and can be used in digital systems to form pulse sequences defining time intervals.

The aim of the invention is to increase reliability by gating the driver of the address codes,

The drawing shows a structural diagram of an apparatus for forming time intervals.

A device for generating time intervals contains a generator of 1 clock pulses, a generator of 2 control pulses} a counter of 3 pulses, a persistent storage device (ROM) 4, a driver of 5 address codes, a multiple input element AND 6, an element OR 7, an element 8 delay and shaper 9 pulses.

The output of the generator 1 is connected to the counting input of the counter 3 and the first input of the driver 9, the output of which is the output of the device, the outputs of the bits of the counter 3 are connected to the inputs of the element 6, the output of which is connected to the second input of the generator 9, with the counting input of the driver 5 address codes and with the first input of the element OR 7, the output of which is connected through the delay element 8 to the installation input of the counter 3, the second input of the element OR 7 is connected to the output of the generator 2 “whose output is connected to the installation input of the generator 5 of the address code The circuit, the outputs of which are connected to the address inputs of the ROM 4, the outputs of which are connected to the inputs of the parallel recording of the counter 3.

The device works as follows.

The control pulse from the generator 2 output goes to the setup input of the address code generator 5 and sets it to the initial state, which is the first address of the ROM 4. The control pulse also flows through the OR element 7 to the delay element 8, which delays the pulse by time , multiple to the integer number of periods of the generator clock frequency required for retrieving information from ROM 4. From the output, delay element 8 impulse goes to the installation input of counter 3, into which a word selected from ROM 4 is written. The number is written th in the ROM 4, smaller values

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neither the time position to be decrypted for the number of clock periods equal to the delay time in the delay element 8. The clock pulses from the output of the generator 1 are fed to the counting input of the counter 3 and the driver 9. The inputs of the element And 6 receive pulses from the outputs of the bits of the counter 3.

When this counter reaches the final state at the output of the AND 6 element, a pulse appears that arrives at the counting input of the shaper 5 address codes, sets the following address of the ROM 4, and through the OR 7 element — at the input of the delay element 8, which delays the counter setting signal 3 night the time of sampling information from the ROM 4.

In the proposed device, the delay value of the output pulse is determined by the delay from the output of the generator 1 to the output of the first discharge of counter 3, which allows the element base to be used with a low fast action.

Claims (1)

Invention Formula A device for forming time intervals, containing a clock pulse generator, the output of which is connected to the first input of the pulse former, the second input of which is connected to the output of the multiple-input element AND, and the first input of the OR element, the second input of which is connected to the output of the control pulse generator, driver address codes, the outputs of which through a permanent storage device are connected to the bit inputs of the pulse counter, the outputs of which are connected to the inputs of the multi-input element AND, exc In order to improve reliability, a delay element is inserted into it, the input of which is connected to the output of the OR element, the output of the delay element is connected to the installation input of a pulse counter, the counting input of which is connected to the output of the clock generator, the output of the multi-input element I is connected to the counting input of the address code generator, the setup input of which is connected to the output of the control pulse generator.