JPS5731145A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5731145A
JPS5731145A JP10657980A JP10657980A JPS5731145A JP S5731145 A JPS5731145 A JP S5731145A JP 10657980 A JP10657980 A JP 10657980A JP 10657980 A JP10657980 A JP 10657980A JP S5731145 A JPS5731145 A JP S5731145A
Authority
JP
Japan
Prior art keywords
psg17
psg
concentration
psg15
si3n4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10657980A
Other languages
Japanese (ja)
Inventor
Toshio Hara
Masanori Sakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10657980A priority Critical patent/JPS5731145A/en
Publication of JPS5731145A publication Critical patent/JPS5731145A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain a high-power protective film, by piling PSG, Si3N4 on an Si substrate, and stacking PSG with a low P concentration as well. CONSTITUTION:PSG15, Si3N416, PSG17 are piled covering a poly Si gate electrode 13. A P concentration in the PSG15 is higher than that in the PSG17, and the concentration in the PSG17 is about 1-8mol percent. By said constitution, the layers 17, 15 become thick barrier layers against external contamination, and no cracks by the internal stress of PSG will occur by the interposition of Si3N4.
JP10657980A 1980-08-01 1980-08-01 Semiconductor device Pending JPS5731145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10657980A JPS5731145A (en) 1980-08-01 1980-08-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10657980A JPS5731145A (en) 1980-08-01 1980-08-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5731145A true JPS5731145A (en) 1982-02-19

Family

ID=14437124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10657980A Pending JPS5731145A (en) 1980-08-01 1980-08-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5731145A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2625839A1 (en) * 1988-01-13 1989-07-13 Sgs Thomson Microelectronics METHOD OF PASSIVATING AN INTEGRATED CIRCUIT

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2625839A1 (en) * 1988-01-13 1989-07-13 Sgs Thomson Microelectronics METHOD OF PASSIVATING AN INTEGRATED CIRCUIT

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