JPS57199045A - Operating circuit - Google Patents

Operating circuit

Info

Publication number
JPS57199045A
JPS57199045A JP8464281A JP8464281A JPS57199045A JP S57199045 A JPS57199045 A JP S57199045A JP 8464281 A JP8464281 A JP 8464281A JP 8464281 A JP8464281 A JP 8464281A JP S57199045 A JPS57199045 A JP S57199045A
Authority
JP
Japan
Prior art keywords
register
circuit
contents
output
shift register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8464281A
Other languages
Japanese (ja)
Inventor
Hiroshi Fujita
Akira Fusaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8464281A priority Critical patent/JPS57199045A/en
Publication of JPS57199045A publication Critical patent/JPS57199045A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To shorten the operation time, by providing registers capable of shifting and counting-up in the operating circuit, where an adding and subtracting circuit is used to perform the division and using the signal from the adding and subtracting circuit to perform the addition or the subtraction between the quotient and the third number simultaneously with the division. CONSTITUTION:In case of the operation of (a/b)+c, a numeric value (a) is set to the first shift register 5, and a numeric value (b) is set to the first register 3, and initial value 0 is set to the third shift register 2, and the register 5 is connected to the register in the first ring connection. Initial value 0 is set to the fourth shift register 10 connected to the register 5 and a gate circuit 8, and the second shift register 11 is connected to the register 10 in the second ring connection. Contents of the register 3 are subtracted from contents of the register 2 by an adding and subtracting circuit 1, and contents of registers 5 and 10 are shifted by the output of the circuit 8 and the operation is repeated when the output of the circuit 1 is negative; and 1 is added to lower bits of the register 10 when the output is positive, thus shortening the operation time.
JP8464281A 1981-06-02 1981-06-02 Operating circuit Pending JPS57199045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8464281A JPS57199045A (en) 1981-06-02 1981-06-02 Operating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8464281A JPS57199045A (en) 1981-06-02 1981-06-02 Operating circuit

Publications (1)

Publication Number Publication Date
JPS57199045A true JPS57199045A (en) 1982-12-06

Family

ID=13836340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8464281A Pending JPS57199045A (en) 1981-06-02 1981-06-02 Operating circuit

Country Status (1)

Country Link
JP (1) JPS57199045A (en)

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