GB2019621A - Improvements in or relating to binary adder circuits - Google Patents

Improvements in or relating to binary adder circuits

Info

Publication number
GB2019621A
GB2019621A GB7908825A GB7908825A GB2019621A GB 2019621 A GB2019621 A GB 2019621A GB 7908825 A GB7908825 A GB 7908825A GB 7908825 A GB7908825 A GB 7908825A GB 2019621 A GB2019621 A GB 2019621A
Authority
GB
United Kingdom
Prior art keywords
input
inputs
binary adder
relating
adder circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7908825A
Other versions
GB2019621B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Priority to GB7908825A priority Critical patent/GB2019621B/en
Publication of GB2019621A publication Critical patent/GB2019621A/en
Application granted granted Critical
Publication of GB2019621B publication Critical patent/GB2019621B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/502—Half adders; Full adders consisting of two cascaded half adders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3868—Bypass control, i.e. possibility to transfer an operand unchanged to the output

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Processing (AREA)

Abstract

A binary adder circuit which, in response to a mode selection signal, is forced to operate as if two of its inputs were equal, irrespective of the actual value of those inputs. In this condition, the circuit acts effectively as a connector, coupling its input C direct to the sum output and the OR of its inputs A, B to the carry output. The invention is useful in a circuit arrangement for performing adding and shifting operations in which with X = 1 and B = 0 for all stages, input A of stage i becomes input (i+1) and hence the sum output of the latter stage. <IMAGE>
GB7908825A 1978-04-25 1979-03-13 Binary adder circuits Expired GB2019621B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB7908825A GB2019621B (en) 1978-04-25 1979-03-13 Binary adder circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1618178 1978-04-25
GB7908825A GB2019621B (en) 1978-04-25 1979-03-13 Binary adder circuits

Publications (2)

Publication Number Publication Date
GB2019621A true GB2019621A (en) 1979-10-31
GB2019621B GB2019621B (en) 1982-02-24

Family

ID=26251877

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7908825A Expired GB2019621B (en) 1978-04-25 1979-03-13 Binary adder circuits

Country Status (1)

Country Link
GB (1) GB2019621B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4718034A (en) * 1984-11-08 1988-01-05 Data General Corporation Carry-save propagate adder

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4718034A (en) * 1984-11-08 1988-01-05 Data General Corporation Carry-save propagate adder
GB2200230A (en) * 1984-11-08 1988-07-27 Data General Corp Carry-save propagate adder
GB2166894B (en) * 1984-11-08 1989-08-02 Data General Corp Carry-save propagate adder
GB2200230B (en) * 1984-11-08 1989-08-02 Data General Corp Carry-save propagate adder

Also Published As

Publication number Publication date
GB2019621B (en) 1982-02-24

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Legal Events

Date Code Title Description
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19940313