KR950006583A - Multiplication Circuits and Methods - Google Patents

Multiplication Circuits and Methods Download PDF

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Publication number
KR950006583A
KR950006583A KR1019930016212A KR930016212A KR950006583A KR 950006583 A KR950006583 A KR 950006583A KR 1019930016212 A KR1019930016212 A KR 1019930016212A KR 930016212 A KR930016212 A KR 930016212A KR 950006583 A KR950006583 A KR 950006583A
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KR
South Korea
Prior art keywords
multiplier
multiplication
last
significant bit
result
Prior art date
Application number
KR1019930016212A
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Korean (ko)
Inventor
신헌기
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019930016212A priority Critical patent/KR950006583A/en
Publication of KR950006583A publication Critical patent/KR950006583A/en

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Abstract

본 발명은 음수 및 양수를 처리하는 곱셈 회로 및 그 방법에 관한 것이다.The present invention relates to a multiplication circuit and a method for processing negative and positive numbers.

본 발명은 승수의 최상위 비트가 1이면 피승수와 승수의 마지막 승산 단계에서 감산기를 선택 수행하고, 승수의 최상위 비트가 0이면 피승수와 승수의 마지막 승산 단계에서 가산기를 선택 수행함으로써, 부호 비트, 비부호 비트에 상관없이 제어가 쉽고 동작 속도가 빠르며 회로가 간단해진다.The present invention selects a subtractor in the multiplicand and the last multiplication step of the multiplier when the most significant bit of the multiplier is 1, and selects an adder in the last multiplication step of the multiplier and the multiplier if the most significant bit of the multiplier is 0, thereby Regardless of the bit, the control is easy, the operation speed is fast, and the circuit is simplified.

Description

곱셈 회로 및 그 방법Multiplication Circuits and Methods

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 곱셈 회로를 나타낸 블럭도.1 is a block diagram showing a conventional multiplication circuit.

제2도는 본 발명에 따른 곱셈 회로를 나타낸 블럭도.2 is a block diagram showing a multiplication circuit according to the present invention.

Claims (2)

피승수와 승수를 승산하는 캐리 새이브 멀티플라이어로 구성된 곱셈 회로에 있어서, 승수의 최상위 비트를 반전시키는 인버터(11)와; 마지막 전단의 피승수와 승수의 승산 결과를 입력으로 제공받고 상기 승수의 최상위 비트를 선택 신호로 하여 상기 마지막 전단의 피승수와 승수의 승산결과를 가산하여 최종값으로 출력하는 전가산기와; 상기 마지막 전단의 피승수와 승수의 승산 결과를 입력으로 제공받고 상기 인버터(11)의 출력을 선택 신호로 하여 상기 마지막 전단의 피승수와 승수의 승산 결과를 감산하여 최종값으로 출력하는 전감산기로 구성되는 곱셈회로.1. A multiplication circuit composed of a carry save multiplier multiplying a multiplier and a multiplier, comprising: an inverter (11) for inverting the most significant bit of the multiplier; A multiplier for receiving a multiplication result of a multiplier of the last front end and a multiplier as input and adding the multiplied result of the multiplier and the multiplier of the last front end as a selection signal and outputting the multiplied result as a final value; A multiplier for receiving the multiplication result of the multiplier of the last front end and the multiplier as an input and subtracting the multiplication result of the multiplier and the multiplier of the last front end as output signals by using the output of the inverter 11 as a selection signal. Multiplication circuit. 피승수와 승수를 승산하는 방법에 있어서, 승수의 최상위 비트가 1이면 피승수와 승수의 마지막 승산 단계에서 뺄셈을 수행하는 스텝과; 승수의 최상위 비트가 0이면 피승수와 승수의 마지막 승산 단계에서 덧셈을 수행하는 스텝으로 이루어지는 곱셈 방법.11. A method for multiplying a multiplicand and a multiplier, the method comprising: subtracting at the last multiplication step of the multiplicand and the multiplier if the most significant bit of the multiplier is 1; A multiplication method comprising the step of performing addition in the multiplication of the multiplier and the last multiplication of the multiplier if the most significant bit of the multiplier is zero. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930016212A 1993-08-20 1993-08-20 Multiplication Circuits and Methods KR950006583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930016212A KR950006583A (en) 1993-08-20 1993-08-20 Multiplication Circuits and Methods

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930016212A KR950006583A (en) 1993-08-20 1993-08-20 Multiplication Circuits and Methods

Publications (1)

Publication Number Publication Date
KR950006583A true KR950006583A (en) 1995-03-21

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KR1019930016212A KR950006583A (en) 1993-08-20 1993-08-20 Multiplication Circuits and Methods

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101243041B1 (en) * 2011-04-08 2013-03-20 한국과학기술원 Multiplier and Multiplication Method Using Hybrid Encoding

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101243041B1 (en) * 2011-04-08 2013-03-20 한국과학기술원 Multiplier and Multiplication Method Using Hybrid Encoding

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