KR101243041B1 - Multiplier and Multiplication Method Using Hybrid Encoding - Google Patents

Abstract

The multiplier according to the present invention receives a multiplier and generates a mode signal generator for generating a first mode signal or a second mode signal according to a bit value of a predetermined area of the multiplier; A hybrid encoder receiving the multiplier and encoding a region including the predetermined region into a first or second radix according to a mode signal generated by the mode signal generator; A partial generator which receives the output of the hybrid encoder and a multiplicand and generates partials; And an adder that sums the parts.

Description

Multiplier and Multiplication Method Using Hybrid Encoding

The present invention relates to multipliers and multiplication methods using hybrid encoding.

Multiplication operations are frequently used in multimedia processors, and boot encoding is now commonly used in multiplication operations. In this case, the encoding of the booth is mainly used for encoding in radix or radix mode.

In this case, when using the 4-base mode encoding, the processing speed is high while the power consumption is high. On the other hand, when using 8-base mode encoding, the processing speed is slow but power consumption is relatively low.

Multiplications require more processing time than addition and subtractions, so it is essential to speed up multiplications in multimedia processors. Therefore, conventionally, a circuit combining a 4-numbered booth encoding multiplier and a Wallace tree tends to be frequently used.

Recently, however, the use of the multimedia processor in a mobile device has been rapidly increasing. There is a limit to the limited power supply in mobile devices.

Accordingly, there is a need for not only speeding up the multiplication operation but also minimizing the use of power consumed in the operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a multiplier and a multiplication operation method capable of minimizing its power consumption while improving the speed of the multiplication operation.

The technical objects to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical subjects which are not mentioned can be clearly understood by those skilled in the art from the description of the present invention .

The multiplier according to the present invention receives a multiplier and generates a mode signal generator for generating a first mode signal or a second mode signal according to a bit value of a predetermined area of the multiplier; A hybrid encoder receiving the multiplier and encoding a region including the predetermined region into a first or second radix according to a mode signal generated by the mode signal generator; A partial generator receiving the output of the hybrid encoder and the multiplicand and generating partials; And an adder that sums the parts.

 The multiplication operation method of the present invention comprises: a mode signal generation step of receiving a multiplier and generating a first mode signal or a second mode signal according to a bit value of a predetermined area of the multiplier; Receiving the multiplier and encoding a region including the predetermined region into a first or second radix according to a mode signal generated by the mode signal generator; Generating partials by receiving an output of the encoding step and a multiplicand; And summing the parts.

According to the present invention, it is possible to provide a multiplier and a multiplication operation method capable of minimizing its power consumption while improving the processing speed of a multiplication operation using hybrid encoding. In addition, according to the present invention, it is possible to provide a multiplier and a multiplication operation method capable of operating for a long time while having high performance.

1 is a block diagram of a multiplier using hybrid encoding according to an embodiment of the present invention.
2 is a table showing a mode signal classification method according to an embodiment of the present invention.
3 is a circuit diagram for implementing a mode signal generator according to an embodiment of the present invention.
4A and 4B illustrate a hybrid encoding method according to an embodiment of the present invention.
5A through 5C are diagrams illustrating an adder included in a multiplier according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. It should be noted that reference numerals and like elements among the drawings are denoted by the same reference numerals as much as possible even if they are shown in different drawings. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

First, a brief description will be given of the encoding method of the 4-base mode and the 8-base mode which are generally used in booth encoding.

In the four-odd mode, the input multiplier is encoded by dividing a region into two bits. Therefore, if the multiplicand and the partial product are generated after the booth encoding is performed in the multiplier mode for the multiplier, the number of partials is reduced by half compared to the case where no booth encoding is performed.

Eight-base mode encodes the multiplier by dividing the multiplier into three bits. Therefore, if the multiplier and the partial are generated after the booth encoding is performed for the multiplier in the eighth mode, the number of the partials is reduced to about one third.

Thus, an additional time for encoding is required, but the number of parts added in the adder subsequently implemented as a Wallace Tree is reduced.

When using 4-base mode encoding, only partial and simple shifts are used, which makes the process very fast. However, since the number of parts is larger than that of the eight cardinal mode, the power consumption is larger than that of the eight cardinal mode.

When 8-base mode encoding is used, the power consumption is lower than that of the 4-base mode, but the processing speed is slower than that of the 4-base mode because a partial occurrence with a multiplier of 3 times occurs in the 8-base mode. That is, in the 8-odd mode, the partial occurrence of the multiplicand of 3 times occurs, and therefore, an addition process is required in the partial generation process, which is slower than the 4-base mode.

The present invention can provide a multiplier and a multiplication operation method including both the advantages of the four-base mode and the advantages of the eight-base mode by hybridly encoding the four-base mode and eight-base mode as described above.

1 is a block diagram of a multiplier using hybrid encoding according to an embodiment of the present invention. The multiplier according to the embodiment of the present invention shown in FIG. 1 may include a mode signal generator 100, a hybrid encoder 200, a partial generator 300, and an adder 400.

The mode signal generator 100 receives a multiplier A and generates a mode signal according to a bit value of a predetermined area of the multiplier A. That is, according to the mode signal generated by the mode signal generator 100, the hybrid encoder 200 performs encoding in the 4-base mode or the 8-base mode.

In the multiplier according to the exemplary embodiment of the present invention, encoding is generally performed in an eight radix mode, but encoding is performed in a four radix mode only when a partial occurrence of a multiplier of three times is generated in the eight radix mode. In other words, the 4-base mode and the 8-base mode are mixed.

2 is a table showing a mode signal classification method according to an embodiment of the present invention. In 8-odd mode, the input multiplier (A) is divided into three bit sections and encoding is performed. In this case, in order to perform 8-odd mode encoding, the lower bits before the zone must be additionally considered in addition to the three bits included in the predetermined zone.

That is, three bits (Xi + 2, Xi + 1, Xi) in the predetermined zone and one bit (Xi-1) before the predetermined zone may be considered to generate a mode signal. The table shown in FIG. 2 shows a partial result generated in the case of a bit value that the four bits (Xi + 2, Xi + 1, Xi and Xi-1) may have.

As shown in Fig. 2, the number of 16 cases occurs according to the value (0 or 1) that the four bits can have. It can be seen that a partial with a multiplicand 3B occurs only in four of the 16 cases. That is, three times the multiplicand occurs only in the case of 1/4.

In the present invention, as described above, encoding is generally performed in an eight radix mode, and encoding is performed in a four radix mode only in a case where 1/4 occurs partially having a multiplier of three times. This eliminates the need for circuitry to perform additional additions. By using the hybrid encoding method as described above, the average number of partial parts can be reduced without slowing down the multiplication operation.

Accordingly, the mode signal generator 100 according to the embodiment of the present invention determines whether a partial multiplier having a multiplier of three times is generated for each input area including three bits with respect to the input multiplier A. FIG. When a partial with a multiply multiplier for a given zone does not occur, a mode signal is transmitted to the hybrid encoder 200 to perform encoding in the 8 odd mode for the zone. If a partial occurrence with a multiplier of 3 times is generated for the predetermined zone, a mode signal for performing encoding in the quadratic mode for the zone is transmitted to the hybrid encoder 200.

As can be seen in the table of FIG. 2, the multiplicative multiplier has only one of the two most significant bits (Xi + 2, Xi + 1) in the region having a value of 1 and the least significant bit (Xi) and the previous bit (in the region). This occurs when only one of Xi-1) has a value of 1.

3 shows an example of a circuit diagram for implementing the mode signal generator 100 according to an embodiment of the present invention. The mode signal generator 100 may include, for example, two XOR logic gates 110 and 120 and one OR logic gate 130. In this case, one of the two XOR logic gates 120 receives the two most significant bits (Xi + 2, Xi + 1), and the other one 110, the least significant bit (Xi) and the previous bit (Xi-1) Is input. Each of the outputs of the two XOR logic gates 110, 120 is input to the OR logic gate 130. In this case, the output of the OR logic gate 130 may represent a mode signal.

At this time, when the output of the OR logic gate 130, that is, the mode signal is "0", it means to encode in 8 odd mode, and when the mode signal is "1", it indicates to encode in 4 odd mode.

The circuit diagram of the mode signal generator 100 shown in FIG. 3 is merely an example and any other configuration may be included.

In this case, the eight radix mode divides the zone by three bits, while the four radix mode divides the zone by two bits. Thus, when encoding in a four-odd mode for a given zone containing three bits, one bit in the zone remains. Therefore, in the case of encoding four bases for a predetermined zone according to an embodiment of the present invention, encoding in four bases can be performed for a wider zone including the predetermined zone.

4A and 4B illustrate an example of a hybrid encoding method according to an embodiment of the present invention. In Fig. 4A, an 8-bit multiplier A is used as an example. This is merely an example and other numbers of bits, such as 16 bits or 32 bits, may be used as the multiplier (A).

First, the 8-bit multiplier A shown in Fig. 4A is zoned by three bits. In this case, three bits are included in each of the first zone and the second zone. At this time, the remaining two bits (X6, X7) are classified into the third zone.

The first zone and the second zone may be encoded in an eight radix mode when no partial with a multiply multiplier occurs. Since only two bits are included in the third zone, the third zone may be encoded in a four-odd mode without determining whether a multiplicative multiplier occurs.

If the first zone is partially multiplied by three times the multiplicative mode encoding may be performed not only for the first zone but also for the second zone. For example, six bits may be an encoding unit. When a multiplicative multiplier occurs in any one zone included in the encoding unit, encoding may be performed in all four bits included in the four radix mode. The encoding unit includes six bits and thus may be divided into three zones when encoding in a four-odd mode.

The encoding unit may have a number of bits in multiples of six. For example, 6 bits, 12 bits, or the like may be included as an encoding unit. It is apparent that the above-described encoding method is merely exemplary and that 4/8 radix hybrid encoding may be performed by another method included in the spirit of the present invention.

The hybrid encoder 200 receives the multiplier A, encodes each of four or eight bases according to a mode signal generated by the mode signal generator 100, and transmits an internal signal to the partial generator 300. do.

The partial generator 300 receives the output of the hybrid encoder 200 and the multiplicand B to generate partials. The parts are input to the adder 400 and summed. The adder 400 may be a wallless tree adder.

5A illustrates an example of implementing an adder 400 included in a multiplier according to an embodiment of the present invention. The adder 400 calculates a final value by adding the first carry unit 410 and the total carry value and the total sum value to generate a total carry value and a total sum value by adding each position of the partial parts. A second adder 420 is included.

The first adder 410 may include a plurality of carry save adder sets 411 according to the number of portions. 5B shows an example of the carry storage adder set 411. The carry preservation adder set 411 may include two carry preservation adders, that is, a first carry preservation adder 412 and a second carry preservation adder 413.

The first carry preserving adder and the second carry preserving adder 412 and 413 may each be a 3-bit carry preserving adder that sums 3-bit inputs and outputs a sum value of 1 bit and a carry value of 1 bit. Three bits a, b, and c are input to the first carry storage adder 412, and a sum value of the first carry storage adder 412 is input to the second carry storage adder 413. The second carry storage adder 413 is input with the other bit d as well as the sum value of the first carry storage adder 412.

The carry preserving adder set 411 shown in Fig. 5B may be used when encoding in the four radix mode is performed in the multiplier according to the embodiment of the present invention.

When the 8 odd mode encoding is performed in the multiplier according to the embodiment of the present invention, power consumption can be reduced by stopping the operation of the second carry storage adder 413 as shown in FIG. 5C.

This is possible because the number of partial portions is reduced when encoding is performed in 8 radix mode as compared to encoding in 4 radix mode. For example, when the multiplier A is 8 bits, four partials occur in the four-odd method while three partial parts occur in the eight-odd method. Therefore, there is no bit d to be input to the second carry storage adder 413. Therefore, even if the second carry storage adder 413 is dynamically turned off, there is no problem in the partial addition operation.

As such, when the second carry storage adder 413 is stopped, the sum value of the first carry storage adder 412 may be designed to bypass the second carry storage adder 413. This bypass may be implemented using a multiplexer (MUX). For example, a 2: 1 MUX using a mode signal generated by a mode signal generator as a control signal may be used to determine whether to add or bypass the sum value of the first carry storage adder 412 to the input of the second carry storage adder. Can be.

The second adder 420 may be a carry propagation adder. The second adder 420 sums the total sum value and the total carry value of the first adder 410 and finally outputs the calculated value of the multiplier.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. will be. Therefore, it should be understood that the above-described embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than the foregoing description, It is intended that all changes and modifications derived from the equivalent concept be included within the scope of the present invention.

100: mode signal generator 200: hybrid encoder
300: partial generator 400: adder

Claims (22)

A mode signal generator that receives a multiplier and generates a first mode signal or a second mode signal according to a bit value of a predetermined area of the multiplier;
A hybrid encoder receiving the multiplier and encoding a region including the predetermined region into a first or second radix according to a mode signal generated by the mode signal generator;
A partial generator receiving the output of the hybrid encoder and the multiplicand and generating partials; And
And a adder for summing the parts. The method of claim 1,
And said first base is 4 bases and said second base is 8 bases. The method of claim 2,
The predetermined zone comprises three consecutive bits in the multiplier,
The mode signal generator is configured to generate the first mode signal when the partial signal having a multiplier of 3 times occurs by inputting the lower 1 bit and the 3 bits of the multiplier immediately before the predetermined region. And generating the second mode signal when the partial with the multiplicand does not occur. The method of claim 3,
When the first mode signal is generated, the hybrid encoder encodes a region including the predetermined region into the fourth radix,
And when the second mode signal is generated, the hybrid encoder encodes the region including the predetermined region into the eight radix. 5. The method of claim 4,
The mode signal generator comprises a first XOR logic gate, a second XOR logic gate, and an OR logic gate,
The first two bits of the predetermined region are input to the first XOR logic gate,
The least significant one bit of the predetermined zone and the lower one bit immediately before the predetermined zone among the multipliers are input to the second XOR logic gate,
An output of the first XOR logic gate and the second XOR logic gate is input to the OR logic gate,
And the mode signal is an output of the OR logic gate. The method of claim 5,
A region comprising the predetermined region is six bits. 7. The method according to any one of claims 1 to 6,
And the adder is a wallless tree adder. The method of claim 7, wherein
The adder may include: a first adder configured to generate a total carry value and a total sum value by adding each position of the portions; And
And a second adder for adding the total carry value and the total sum value to output a final calculation value. 9. The method of claim 8,
The first adder includes a plurality of carry preservation adder sets,
And each of said carry preservation adder sets comprises a first carry preservation adder and a second carry preservation adder. 10. The method of claim 9,
The first and second carry preserving adders are 3-bit carry preserving adders each of which adds a 3-bit input and outputs a 1-bit sum value and a 1-bit carry value.
And a sum value of the first carry storage adder is input to the second carry storage adder. The method of claim 10,
The second radix is eight radix,
And the operation of the second carry preserving adder is stopped when the encoder encodes the second radix. The method of claim 10,
And the second adder is a carry propagation adder. A mode signal generation step of receiving a multiplier and generating a first mode signal or a second mode signal according to a bit value of a predetermined area of the multiplier;
Receiving the multiplier and encoding a region including the predetermined region into a first or second radix according to a mode signal generated by the mode signal generator;
Generating partials by receiving an output of the encoding step and a multiplicand; And
Multiplying the partials. The method of claim 13,
And the first base is 4 bases and the second base is 8 bases. 15. The method of claim 14,
The predetermined zone comprises three consecutive bits in the multiplier,
The mode signal generation step is:
The first mode signal is generated when the partial one having a multiplier of three times occurs by inputting the lower one bit and the three bits immediately before the predetermined area among the multipliers. And if not generated, generating the second mode signal. 16. The method of claim 15,
The encoding step is:
When the first mode signal is generated, an area including the predetermined area is encoded into the fourth cardinal number,
And multiplying an area including the predetermined area into the eight radix when the second mode signal is generated. 17. The method of claim 16,
And the region including the predetermined region is 6 bits. 18. The method according to any one of claims 13 to 17,
The summing step is:
A first summing step of adding a total carry value and a total sum value by adding each portion of the portions; And
And a second summing step of generating a final calculated value by summing the total carry value and the total sum value. 19. The method of claim 18,
The first summing step is performed by a plurality of carry preservation adder sets,
And each of the carry storage adder sets comprises a first carry storage adder and a first carry storage adder. 20. The method of claim 19,
The first and second carry preserving adders are 3-bit carry preserving adders each of which adds a 3-bit input and outputs a 1-bit sum value and a 1-bit carry value.
And the first adding step includes inputting a sum value of the first carry storage adder into the second carry storage adder. 21. The method of claim 20,
The second radix is eight radix,
When encoding in the second step in the encoding step,
And the operation of the second carry storage adder is stopped, and the sum of the first carry storage adder bypasses the second carry storage adder in the first adding step. The method of claim 21,
And said second summing step is performed by a carry propagation adder.

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