JPS57190341A - Circuit borad composition - Google Patents
Circuit borad compositionInfo
- Publication number
- JPS57190341A JPS57190341A JP56074255A JP7425581A JPS57190341A JP S57190341 A JPS57190341 A JP S57190341A JP 56074255 A JP56074255 A JP 56074255A JP 7425581 A JP7425581 A JP 7425581A JP S57190341 A JPS57190341 A JP S57190341A
- Authority
- JP
- Japan
- Prior art keywords
- gold
- tin alloy
- electrodes
- plating
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H10W70/60—
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56074255A JPS57190341A (en) | 1981-05-19 | 1981-05-19 | Circuit borad composition |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56074255A JPS57190341A (en) | 1981-05-19 | 1981-05-19 | Circuit borad composition |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57190341A true JPS57190341A (en) | 1982-11-22 |
| JPS6342852B2 JPS6342852B2 (cg-RX-API-DMAC10.html) | 1988-08-25 |
Family
ID=13541854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56074255A Granted JPS57190341A (en) | 1981-05-19 | 1981-05-19 | Circuit borad composition |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57190341A (cg-RX-API-DMAC10.html) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
| US6333554B1 (en) | 1997-09-08 | 2001-12-25 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102235020B1 (ko) * | 2013-07-03 | 2021-04-02 | 루미리즈 홀딩 비.브이. | 금속화 층 아래에 스트레스-버퍼 층을 가지는 led |
-
1981
- 1981-05-19 JP JP56074255A patent/JPS57190341A/ja active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208186A (en) * | 1989-02-09 | 1993-05-04 | National Semiconductor Corporation | Process for reflow bonding of bumps in IC devices |
| US6333554B1 (en) | 1997-09-08 | 2001-12-25 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6344690B1 (en) | 1997-09-08 | 2002-02-05 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6495441B2 (en) | 1997-09-08 | 2002-12-17 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6786385B1 (en) | 1997-09-08 | 2004-09-07 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6342852B2 (cg-RX-API-DMAC10.html) | 1988-08-25 |
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