JPS57189250A - Binary multiplication circuit - Google Patents

Binary multiplication circuit

Info

Publication number
JPS57189250A
JPS57189250A JP7513581A JP7513581A JPS57189250A JP S57189250 A JPS57189250 A JP S57189250A JP 7513581 A JP7513581 A JP 7513581A JP 7513581 A JP7513581 A JP 7513581A JP S57189250 A JPS57189250 A JP S57189250A
Authority
JP
Japan
Prior art keywords
shift register
register
content
multiplication
significant bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7513581A
Other languages
Japanese (ja)
Inventor
Tsukasa Kudo
Akira Fusaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7513581A priority Critical patent/JPS57189250A/en
Publication of JPS57189250A publication Critical patent/JPS57189250A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To decrease the time for operation processing, by executing the multiplication among three inputs with one multiplication through the connection in series of the similar operation circuit to an operation circuit making addition through the use of two adders and multification through the use of a shift register. CONSTITUTION:A multiplicand (a), 1st multiplier (b) and 2nd multiplier (c) consisting of an n-bit one word through the use of two adders 6 and 22 are stored in the 1st register 1, 1st shift register 2 and 2nd register 18, and after 1 or 0 is multiplied with th content of the register 1 according to the logic of the least significant bit 5 of the shift register 2, the result is added with the content of the 2nd shift register 3 with an adder 6 and stored in the 2nd shift register 3. Since the least significant bit of the register 3 is the least significant bit of (a*b), according to the logic of the least significant bit, after 1 or 0 is multiplied with the content of the 2nd shift register 18, the result is added with the content of the 3rd shift register 19 and stored in the 3rd shift register 19, and the multiplication among three inputs can be made by one multiplication by completing all the operations when the content of a loop counter 8 is 2n.
JP7513581A 1981-05-19 1981-05-19 Binary multiplication circuit Pending JPS57189250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7513581A JPS57189250A (en) 1981-05-19 1981-05-19 Binary multiplication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7513581A JPS57189250A (en) 1981-05-19 1981-05-19 Binary multiplication circuit

Publications (1)

Publication Number Publication Date
JPS57189250A true JPS57189250A (en) 1982-11-20

Family

ID=13567439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7513581A Pending JPS57189250A (en) 1981-05-19 1981-05-19 Binary multiplication circuit

Country Status (1)

Country Link
JP (1) JPS57189250A (en)

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