JPS57171844A - Phase detecting circuit in phase locked loop - Google Patents
Phase detecting circuit in phase locked loopInfo
- Publication number
- JPS57171844A JPS57171844A JP56057660A JP5766081A JPS57171844A JP S57171844 A JPS57171844 A JP S57171844A JP 56057660 A JP56057660 A JP 56057660A JP 5766081 A JP5766081 A JP 5766081A JP S57171844 A JPS57171844 A JP S57171844A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- phase
- delaying
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To prevent erroneous generation of a phase detecting signal, by constituting so that one input signal has wider pulse width than that of the other, between 2 input signals supplied to a phase comparator provided in a phase locked loop. CONSTITUTION:A delaying circuit 10 obtains a reference signal fi' by delaying an input signal fi by a prescribed time. On the other hand, a comparing signal fo' is obtained by providing a delaying circuit 11 for delaying an input signal fo inputted to a phase comparator 2 from a voltage control oscillating circuit 4, by a time decided in advance, and taking OR of an output signal of the circuit 11 and the signal fo by an OR circuit 12. Subsequently, the output of the circuit 12 is converted as to its polarity by an invertor 13, NOT OR of each output signal of the invertor 13 and the circuit 10 is taken by an NAND circuit 14, and a phase detecting signal is outputted to an output terminal 15 from the circuit 14. In this case, a phase difference is detected by making phase of the input signals fi, fo have a tolerance.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56057660A JPS57171844A (en) | 1981-04-16 | 1981-04-16 | Phase detecting circuit in phase locked loop |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56057660A JPS57171844A (en) | 1981-04-16 | 1981-04-16 | Phase detecting circuit in phase locked loop |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57171844A true JPS57171844A (en) | 1982-10-22 |
Family
ID=13062047
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56057660A Pending JPS57171844A (en) | 1981-04-16 | 1981-04-16 | Phase detecting circuit in phase locked loop |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57171844A (en) |
-
1981
- 1981-04-16 JP JP56057660A patent/JPS57171844A/en active Pending
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