JPS5698933A - Phase comparator - Google Patents
Phase comparatorInfo
- Publication number
- JPS5698933A JPS5698933A JP128180A JP128180A JPS5698933A JP S5698933 A JPS5698933 A JP S5698933A JP 128180 A JP128180 A JP 128180A JP 128180 A JP128180 A JP 128180A JP S5698933 A JPS5698933 A JP S5698933A
- Authority
- JP
- Japan
- Prior art keywords
- input
- signal
- taken
- circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
- G01R25/04—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents involving adjustment of a phase shifter to produce a predetermined phase difference, e.g. zero difference
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To enable stable operation even to the input signal with phase difference of zero, by the constitution of the circuit that the S and R input signals of R-SFF are always 1 and 0, when the phase difference between two input signals is zero. CONSTITUTION:One input of an AND circuit 3 is taken as an error signal, and another input is taken as a signal in which this error signal is delayed by pulse width PWs and the amplitude is inverted with the inverter type delay element 2. One input of an AND circuit 3' is taken as the reference signal, and another input signal is taken as the signal in which it is delayed by the pulse width PWR and the amplitude is inverted. Setting is made by PWS>>PWR, and one input to the AND circuit 3'' is the output of an NAND circuit 9 being both the inputs of the output signal of the circuits 3, 3', and another input is taken as the output signal to the circuit 3'. The output signals of the circuits 3, 3'' are taken respectively as the inputs of S and R side of R-SFF5. Thus, when the phase difference between the input signal at the terminals 1 and 7 is zero, S and R signals of R-SFF are always 1 and 0, then the Q output of FF5 is not instable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP128180A JPS5698933A (en) | 1980-01-11 | 1980-01-11 | Phase comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP128180A JPS5698933A (en) | 1980-01-11 | 1980-01-11 | Phase comparator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5698933A true JPS5698933A (en) | 1981-08-08 |
Family
ID=11497061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP128180A Pending JPS5698933A (en) | 1980-01-11 | 1980-01-11 | Phase comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5698933A (en) |
-
1980
- 1980-01-11 JP JP128180A patent/JPS5698933A/en active Pending
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