JPS57166646A - Logical circuit - Google Patents

Logical circuit

Info

Publication number
JPS57166646A
JPS57166646A JP56051980A JP5198081A JPS57166646A JP S57166646 A JPS57166646 A JP S57166646A JP 56051980 A JP56051980 A JP 56051980A JP 5198081 A JP5198081 A JP 5198081A JP S57166646 A JPS57166646 A JP S57166646A
Authority
JP
Japan
Prior art keywords
asynchronous
synchronous
case
register
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56051980A
Other languages
English (en)
Inventor
Shigeru Takasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56051980A priority Critical patent/JPS57166646A/ja
Publication of JPS57166646A publication Critical patent/JPS57166646A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP56051980A 1981-04-07 1981-04-07 Logical circuit Pending JPS57166646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56051980A JPS57166646A (en) 1981-04-07 1981-04-07 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56051980A JPS57166646A (en) 1981-04-07 1981-04-07 Logical circuit

Publications (1)

Publication Number Publication Date
JPS57166646A true JPS57166646A (en) 1982-10-14

Family

ID=12902003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56051980A Pending JPS57166646A (en) 1981-04-07 1981-04-07 Logical circuit

Country Status (1)

Country Link
JP (1) JPS57166646A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62174670A (ja) * 1985-10-23 1987-07-31 テキサス　インスツルメンツ　インコ−ポレイテツド 論理回路のテストに使用する回路
JPS63107160A (ja) * 1986-10-24 1988-05-12 Nec Corp 内部にスル−パス機能を持つパツケ−ジ検査容易化ｌｓｉ
JPH0511027A (ja) * 1991-07-04 1993-01-19 Sharp Corp スキヤン回路を内蔵した集積回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62174670A (ja) * 1985-10-23 1987-07-31 テキサス　インスツルメンツ　インコ−ポレイテツド 論理回路のテストに使用する回路
JPS63218881A (ja) * 1985-10-23 1988-09-12 テキサス　インスツルメンツ　インコーポレイテツド テスト可能な論理回路
JPS63107160A (ja) * 1986-10-24 1988-05-12 Nec Corp 内部にスル−パス機能を持つパツケ−ジ検査容易化ｌｓｉ
JPH0511027A (ja) * 1991-07-04 1993-01-19 Sharp Corp スキヤン回路を内蔵した集積回路

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