JPS57157560A - Semiconductor integrated memory and using method thereof - Google Patents

Semiconductor integrated memory and using method thereof

Info

Publication number
JPS57157560A
JPS57157560A JP56042186A JP4218681A JPS57157560A JP S57157560 A JPS57157560 A JP S57157560A JP 56042186 A JP56042186 A JP 56042186A JP 4218681 A JP4218681 A JP 4218681A JP S57157560 A JPS57157560 A JP S57157560A
Authority
JP
Japan
Prior art keywords
layer
electrode
fet
type
type diffused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56042186A
Other languages
Japanese (ja)
Inventor
Susumu Kurosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56042186A priority Critical patent/JPS57157560A/en
Publication of JPS57157560A publication Critical patent/JPS57157560A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain a memory having high density, large capacity and stable operation without forward bias of P-N junction by employing two complementary type FET cells. CONSTITUTION:A memory cell formed of two-layer polycrystalline Si gate process is shown in plane and sectional divisions, and the number in the plane division corresponding to the number in the sectional division is represented by a parenthesis. That is, P<+> type diffused layer 61(51) operating also as the first electrode of a P-channel first MOSFET and writing bit lies W, W'; gates 62(52) of the FET; N type diffused layer 64(54) forming the first electrode of an N- channel second MOSFET connected to polycrystalline Si reading bit lines R, R', gate 65(55) of the FET, and P type diffused layer 66(56) are formed in an N type semiconductor substrate 63, and insulator films 68-70 are covered on the prescribed region. With this structure, the prescribed voltage is precharged in the layer 64 becoming the first electrode, thereby suppressing the variation in the voltage of the layer 66 of electrically floated state.
JP56042186A 1981-03-23 1981-03-23 Semiconductor integrated memory and using method thereof Pending JPS57157560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56042186A JPS57157560A (en) 1981-03-23 1981-03-23 Semiconductor integrated memory and using method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56042186A JPS57157560A (en) 1981-03-23 1981-03-23 Semiconductor integrated memory and using method thereof

Publications (1)

Publication Number Publication Date
JPS57157560A true JPS57157560A (en) 1982-09-29

Family

ID=12628966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56042186A Pending JPS57157560A (en) 1981-03-23 1981-03-23 Semiconductor integrated memory and using method thereof

Country Status (1)

Country Link
JP (1) JPS57157560A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4998976A (en) * 1972-12-29 1974-09-19
JPS5534348A (en) * 1978-08-31 1980-03-10 Fujitsu Ltd Semiconductor memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4998976A (en) * 1972-12-29 1974-09-19
JPS5534348A (en) * 1978-08-31 1980-03-10 Fujitsu Ltd Semiconductor memory device

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