JPS57153445A - Sos semiconductor substrate - Google Patents

Sos semiconductor substrate

Info

Publication number
JPS57153445A
JPS57153445A JP3849281A JP3849281A JPS57153445A JP S57153445 A JPS57153445 A JP S57153445A JP 3849281 A JP3849281 A JP 3849281A JP 3849281 A JP3849281 A JP 3849281A JP S57153445 A JPS57153445 A JP S57153445A
Authority
JP
Japan
Prior art keywords
substrate
visible ray
thickness
layer
sapphire substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3849281A
Other languages
Japanese (ja)
Inventor
Yoshio Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3849281A priority Critical patent/JPS57153445A/en
Publication of JPS57153445A publication Critical patent/JPS57153445A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)

Abstract

PURPOSE:To enable the detection of a wafer by a visible ray while preventing the cracking of a sapphire substrate due to thermal strain by also forming an Si layer previously onto the back of the substrate when the SOS semiconductor substrate is manufactured by shaping an SI layer onto the surface of the sapphire substrate. CONSTITUTION:The single crystal silicon layer is grown on the surface of the sapphire substrate 1 with approximately 0.4mm. thickness in 0.3-2mum thickness, and the back of the substrate 1 is also coated with the silicon layer 3 through a gaseous phase growth method or sputtering. Thickness opaque to the visible ray is selected in the silicon layers at that time. Accordingly, the water can be detected by the visible ray, and the warp of the substrate and cracking due to rapid heating and cooling can also be prevented because the layers 2, 3 give force in the opposite direction to the substrate 1.
JP3849281A 1981-03-17 1981-03-17 Sos semiconductor substrate Pending JPS57153445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3849281A JPS57153445A (en) 1981-03-17 1981-03-17 Sos semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3849281A JPS57153445A (en) 1981-03-17 1981-03-17 Sos semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS57153445A true JPS57153445A (en) 1982-09-22

Family

ID=12526755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3849281A Pending JPS57153445A (en) 1981-03-17 1981-03-17 Sos semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS57153445A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0676794A2 (en) * 1994-04-07 1995-10-11 International Business Machines Corporation Method for fabricating a silicon-on-sapphire wafer
WO2002043130A3 (en) * 2000-11-25 2002-09-06 Dalsa Semiconductor Inc Method of making a functional device with deposited layers subject to high temperature anneal
EP1347319A3 (en) * 2002-03-21 2004-11-24 Dalsa Semiconductor Inc. Method of making photonic devices with Spin-On-Glass interlayer
WO2004095554A3 (en) * 2003-04-18 2004-12-23 Raytheon Co Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion
JP2006147788A (en) * 2004-11-18 2006-06-08 Oki Electric Ind Co Ltd Structure of semiconductor device and its manufacturing method
JP2006261556A (en) * 2005-03-18 2006-09-28 Oki Electric Ind Co Ltd Sos wafer and its manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5057381A (en) * 1973-09-19 1975-05-19
JPS50159255A (en) * 1974-06-11 1975-12-23

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5057381A (en) * 1973-09-19 1975-05-19
JPS50159255A (en) * 1974-06-11 1975-12-23

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0676794A3 (en) * 1994-04-07 1995-11-29 Ibm Method for fabricating a silicon-on-sapphire wafer.
US5877094A (en) * 1994-04-07 1999-03-02 International Business Machines Corporation Method for fabricating a silicon-on-sapphire wafer
US6238935B1 (en) 1994-04-07 2001-05-29 International Business Machines Corporation Silicon-on-insulator wafer having conductive layer for detection with electrical sensors
EP0676794A2 (en) * 1994-04-07 1995-10-11 International Business Machines Corporation Method for fabricating a silicon-on-sapphire wafer
WO2002043130A3 (en) * 2000-11-25 2002-09-06 Dalsa Semiconductor Inc Method of making a functional device with deposited layers subject to high temperature anneal
US6937806B2 (en) 2002-03-21 2005-08-30 Dalsa Semiconductor Inc. Method of making photonic devices with SOG interlayer
EP1347319A3 (en) * 2002-03-21 2004-11-24 Dalsa Semiconductor Inc. Method of making photonic devices with Spin-On-Glass interlayer
WO2004095554A3 (en) * 2003-04-18 2004-12-23 Raytheon Co Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion
US6884645B2 (en) 2003-04-18 2005-04-26 Raytheon Company Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion
JP2006523960A (en) * 2003-04-18 2006-10-19 レイセオン・カンパニー Method for processing a device structure having an attached wafer structure on a composite substrate having a matched coefficient of thermal expansion
JP2006147788A (en) * 2004-11-18 2006-06-08 Oki Electric Ind Co Ltd Structure of semiconductor device and its manufacturing method
JP2006261556A (en) * 2005-03-18 2006-09-28 Oki Electric Ind Co Ltd Sos wafer and its manufacturing method
US7564100B2 (en) 2005-03-18 2009-07-21 Oki Semiconductor Co., Ltd. Silicon on sapphire wafer
US7989324B2 (en) 2005-03-18 2011-08-02 Oki Semiconductor Co., Ltd. Method for manufacturing silicon on sapphire wafer

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